DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-6 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/26/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication Number 2017/0330889 A1 to Richter et al., “Richter”.
Regarding claim 7, Richter discloses a method for fabricating a semiconductor device (e.g. FIG. 4a), the method comprising:
forming (e.g. FIG. 2a) a gate stack on a substrate, the gate stack (201, left side) comprising a floating gate (106, ¶ [0033]) and a control gate (110, ¶ [0034]);
forming (e.g. FIG. 2a) a select gate insulating layer (120, ¶ [0037]) on a sidewall of the gate stack;
forming (Fig. 2a, FIG. 4a) a select gate (204, part of 301 ¶ [0042]-[0044]) on the select gate insulating layer, the select gate having a height higher than a height of the gate stack (as pictured);
forming spacers (multiple instances of 305 and 401, ¶ [0055],[0056],[0067]) on substrate, the spacers comprising:
a first spacer (e.g. 305 on far left on side of 204, see Examiner-annotated figure below) disposed on a sidewall of the select gate;
a second spacer (305 above 110, see Examiner-annotated figure below) disposed on an opposite sidewall of the select gate, and extending on a top surface of the gate stack;
a third spacer (305 on side of 110, see Examiner-annotated figure above) disposed on an opposite sidewall of the gate stack; and
forming a source region and a drain region (regions 402 and 104, ¶ [0068],[0031]) adjacent to the first spacer and third spacer, respectively (wherein “adjacent” is interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) as being in proximity and not requiring alignment).
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Regarding claim 12, Richter discloses a method for fabricating a semiconductor device (e.g. FIG. 4a), the method comprising:
forming (e.g. FIG. 2a) a gate stack (201, left side) on a substrate, the gate stack comprising a floating gate (106, ¶ [0033]) and a control gate (110, ¶ [0034]);
forming (e.g. FIG. 2a) a select gate insulating layer (120, ¶ [0037]) on a sidewall of the gate stack;
forming (Fig. 2a, FIG. 4a) a select gate (204, part of 301 ¶ [0042]-[0044]) on the select gate insulating layer, the select gate having a first height (over 106 and 110) higher than a height of the gate stack and a second height (to the left) being similar to that of the gate stack (see Examiner-annotated figure above);
forming (FIG. 4a) lightly doped regions (306, ¶ [0057]) in the substrate;
forming spacers (multiple instances of 305 and 401, ¶ [0055],[0056],[0067]) on substrate, the spacers comprising:
a first spacer (e.g. 305 on far left on side of 204, see Examiner-annotated figure above) disposed on a sidewall of the select gate (204, part of 301);
a second spacer (305 above 110, see Examiner-annotated figure above) disposed on an opposite sidewall of the select gate, and extending on a top surface of the gate stack (above 106 and 110); and
a third spacer (305 on side of 110, see Examiner-annotated figure above) disposed on an opposite sidewall of the gate stack; and
forming a source region and a drain region (regions 402 and 104, ¶ [0068],[0031]) adjacent to the first spacer and third spacer (wherein “adjacent” is interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) as being in proximity and not requiring alignment).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0366551 A1 to Fang et al., “Fang”, in view of U.S. Patent Application Publication Number 2014/0097480 A1 to Shum et al., “Shum”.
Regarding claim 7, Fang discloses a method for fabricating a semiconductor device (e.g. FIG. 12), the method comprising:
forming (FIG. 14A) a gate stack on a substrate, the gate stack comprising a charge storage structure (1408, ¶ [0107]) and a control gate (1410);
forming (FIG. 14B) a select gate insulating layer (1426, ¶ [0108]) on a sidewall of the gate stack;
forming (FIG. 14C to 14F) a select gate (1434 becomes SG 1432, ¶ [0110],[0111]) on the select gate insulating layer, the select gate having a height higher (after removing 1420 in FIG. 14F) than a height of the gate stack (height of 1410);
forming (FIG. 14F) spacers (1442,1442a) on substrate, the spacers comprising:
a first spacer (1442 on far left) disposed on a sidewall of the select gate;
a second spacer (1442a, ¶ [0111]) disposed on an opposite sidewall of the select gate, and extending on a top surface of the gate stack (above 1410);
a third spacer (1442 on sidewall of MG 1410) disposed on an opposite sidewall of the gate stack; and
forming (FIG. 14G) a source region (1440, ¶ [0112]) and a drain region (1436, ¶ [0112]) adjacent to the first spacer and third spacer, respectively (wherein “adjacent” is interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) as being in proximity and not requiring alignment).
Although Fang suggests wherein other charge storage structures may include a floating gate may (¶ [0100]), Fang fails to clearly teach in the embodiment of FIG. 12 wherein the charge storage structure (1408) is a floating gate or including a floating gate with the charge storage structure.
Shum teaches (e.g. FIG 3D) wherein a charge storage structure (206) may be a floating gate ([0027],[0033],[0040],[0046],[0049]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Fang by forming the charge storage structure as a floating gate as taught by Shum since the majority of non-volatile memory cells like EEPROM (Electrically Erasable Programmable Read Only Memory) or flash memory cells include either a floating gate or charge trapping layer as the charge storage element (Shum ¶ [0027]) and
since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case one having ordinary skill in the art could have applied (B) simple substitution of a floating gate for the charge trapping element of Fang with the predictable and desired result of forming a suitable charge storage for the non-volatile memory cell and it would have been obvious to one having ordinary skill in the art to have applied simple substitution based on the teachings of Shum which teaches both charge trapping and floating gates as interchangeable (¶ [0027],[0033],[0040],[0046],[0049])
Regarding claim 8, Fang in view of Shum yields the method of claim 7, and Fang further teaches:
forming (FIG. 14A) a stacked layer (including 1410) on the substrate;
forming (FIG. 14A) a hard mask pattern (1420, ¶ [0107]) on the stacked layer; and
performing an etching process (“etching techniques” ¶ [0107]) to the stacked layer implemented by the hard mask pattern to form the gate stack.
Regarding claim 9, Fang in view of Shum yields the method of claim 7, and Fang further teaches:
forming (FIG. 14G) a select gate silicide layer (1444, ¶ [0112]) on the select gate (1432); and
forming (FIG. 14G) a control gate silicide layer (1444) on the control gate (1410), the control gate silicide layer (1444 on 1410) having a lateral length smaller than a lateral length of the control gate (due to spacer 1442a).
Regarding claim 10, Fang in view of Shum yields the method of claim 9, and Fang further teaches wherein the second spacer (1442a) is disposed between the select gate silicide layer (1444 on SG 1432) and the control gate silicide layer (1444 on MG 1410).
Regarding claim 11, Fang in view of Shum yields the method of claim 7, and Fang further teaches wherein the second spacer (1442a) has a height higher (as pictured) than a height of the first spacer (1442 on SG 1432) or a height of the third spacer (1444 on MG 1410).
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0366551 A1 to Fang et al., “Fang”, in view of U.S. Patent Application Publication Number 2014/0097480 A1 to Shum et al., “Shum”, further in view of U.S. Patent Application Publication Number 2010/0163965 A1 to Kwon, “Kwon”.
Regarding claim 12, Fang discloses a method for fabricating a semiconductor device (e.g. FIG. 12), the method comprising:
forming (FIG. 14A) a gate stack on a substrate, the gate stack comprising a charge storage structure (1408, ¶ [0107]) and a control gate (1410);
forming (FIG. 14B) a select gate insulating layer (1426, ¶ [0108]) on a sidewall of the gate stack;
forming (FIG. 14C to 14F) a select gate (1434 becomes SG 1432, ¶ [0110],[0111]) on the select gate insulating layer, the select gate having a first height higher than a height of the gate stack and a second height being similar to that of the gate stack (see Examiner-annotated figure below);
forming (FIG. 14F) spacers (1442,1442a) on substrate, the spacers comprising:
a first spacer (1442 on far left) disposed on a sidewall of the select gate;
a second spacer (1442a, ¶ [0111]) disposed on an opposite sidewall of the select gate, and extending on a top surface of the gate stack (above 1410); and
a third spacer (1442 on sidewall of MG 1410) disposed on an opposite sidewall of the gate stack; and
forming (FIG. 14G) a source region (1440, ¶ [0112]) and a drain region (1436, ¶ [0112]) adjacent to the first spacer and third spacer, respectively (wherein “adjacent” is interpreted under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) as being in proximity and not requiring alignment).
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Although Fang suggests wherein other charge storage structures may include a floating gate may (¶ [0100]), Fang fails to clearly teach in the embodiment of FIG. 12 wherein the charge storage structure (1408) is a floating gate or including a floating gate with the charge storage structure.
Shum teaches (e.g. FIG 3D) wherein a charge storage structure (206) may be a floating gate ([0027],[0033],[0040],[0046],[0049]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Fang by forming the charge storage structure as a floating gate as taught by Shum since the majority of non-volatile memory cells like EEPROM (Electrically Erasable Programmable Read Only Memory) or flash memory cells include either a floating gate or charge trapping layer as the charge storage element (Shum ¶ [0027]) and
since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case one having ordinary skill in the art could have applied (B) simple substitution of a floating gate for the charge trapping element of Fang with the predictable and desired result of forming a suitable charge storage for the non-volatile memory cell and it would have been obvious to one having ordinary skill in the art to have applied simple substitution based on the teachings of Shum which teaches both charge trapping and floating gates as interchangeable (¶ [0027],[0033],[0040],[0046],[0049])
Fang fails to clearly teach forming lightly doped regions in the substrate.
Kwon teaches (e.g. FIG. 2) forming lightly doped regions (31, ¶ [0076]) in the substrate (10).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Fang in view of Shum with lightly doped LDD region(s) as taught by Kwon in order to improve hot carrier injection (HTL) efficiency (Kwon ¶ [0076]).
Regarding claim 13, Fang in view of Shum and Kwon yields the method of claim 12, and Fang further teaches:
forming (FIG. 14G) a select gate silicide layer (1444, ¶ [0112]) on the select gate (1432); and
forming (FIG. 14G) a control gate silicide layer (1444) on the control gate (1410), the control gate silicide layer (1444 on 1410) having a lateral length smaller than a lateral length of the control gate (due to spacer 1442a).
Regarding claim 14, Fang in view of Shum and Kwon yields the method of claim 13, and Fang further teaches (FIG. 12) depositing an interlayer insulating layer (1232a,1232b, ¶ [0113]) on the gate stack;
forming (FIG. 12) contact plugs (1234, ¶ [0113]) in the interlayer insulating layer; and
electrically connecting metal wirings (1236, 1238, ¶ [0113], similar to Applicant’s 441,442,443) to the contact plugs.
Regarding claim 15, although Fang in view of Shum and Kwon yields the method of claim 12, Fang fails to clearly state in sufficient detail for anticipation wherein an upper surface area of the select gate (SG 1210) is larger than that of the gate stack (MG 1212).
However, Fang teaches in the drawings (e.g. FIG. 12) wherein the lateral width of the upper surface of the select gate (SG 1210) is pictured to be wider than the lateral width of the upper surface of the gate stack (MG 1212).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Fang in view of Shum and Kwon with the surface area of the select gate larger than that of the gate stack as suggested by the drawings of Fang since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the surface area is determined by the dimensions of the select gate and gate stack which determine the relative dimensions and electrical characteristics of the gates making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891