Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 067237-2306
Filling Date: 10/10/23
Priority Date: 11/24/22 (not perfected)
Inventor: Suzumura et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Foreign Priority
Foreign Priority did not perfect.
Claim Objections
Claims 1 and 18 are objected to because of the following informalities:
Claim 18 recites “the semiconductor layer located in the region”. However, it should be “the semiconductor layer located in the first region”.
Claim 18 recites “the semiconductor located in the first region has:”. However, it should be “the semiconductor layer located in the first region has:”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 8, 13, 15 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto US 2022/0157863 A1).
Regarding claim 1, Yamamoto discloses a semiconductor device (e.g. Fig.29) comprising:
a substrate 1 (para[0047]);
a resistance element 3 (para[0051]) formed in
a first region 1B (para[0050]) of the substrate 1; and
a MISFET 2 (para[0045]) formed in
a second region 1A (para[0050]) of the substrate 1, wherein the substrate 1 has:
a support substrate SB (para[0047]);
an insulating layer BX (para[0047]) on the support substrate SB; and
a semiconductor layer SM (para[0051]) on the insulating layer BX, wherein the resistance element 3 is comprised of: the semiconductor layer SM located in the first region 1B; and
an epitaxial semiconductor layer EP (para[0056]) formed on the semiconductor layer (SM) located in the first region 1B, wherein the epitaxial semiconductor layer EP has:
a first semiconductor portion EP2a (para[0064]) formed on the semiconductor layer SM located in the first region 1B; and
a second semiconductor portion EP2b (para[0064]) formed on the semiconductor layer SM located in the first region 1B, and spaced apart (Fig.29) from the first semiconductor portion EP2a, wherein the semiconductor layer SM located in the first region 1B has:
a first connection portion (EP2a portion of SMb) on which the first semiconductor portion EP2a is formed;
a second connection portion (EP2b portion of SMb) on which the second semiconductor portion EP2b is formed; and
an element portion (portion of SM) located between the first connection portion EP2a and the second connection portion EP2b and, on which no epitaxial semiconductor layer (Fig.15) is formed,
wherein a conductivity type (n-type; para[0096], Fig.16) of each of the first semiconductor portion (EP2a), the second semiconductor portion (EP2b), the first connection portion (EP2a portion of SMb), the second connection portion (EP2b portion of SMb), and the element portion (SMb portion) is a first conductivity type (n-type),
wherein each of the first connection portion (EP2a portion of SMb) and the second connection portion (EP2b portion of SMb) further has
a first low concentration region (Fig.16; para[0096]; without n-type impurity implanted in EP2a/EP2b of SMb region, so they have low concentration) of the first conductivity type (n-type), which is located next to (Fig.29) the element portion 3,
wherein each of the first semiconductor portion (EP2a) and the second semiconductor portion (Ep2b) further has a first medium concentration region (Fig.16; para[0096]; due to the n-type implant) of the first conductivity type, which is located on the first low concentration region,
wherein an impurity concentration of the first low concentration region of each of the first connection portion and the second connection portion is lower than an impurity concentration of the element portion (since Fig.16 shows implant in the exposed element portion of SMb, impurity is higher in the element region), and
wherein an impurity concentration of the first medium concentration region of each of the first semiconductor portion (EP2a) and the second semiconductor portion (EP2b) is higher (due to the n-type implant shown in Fig.16, para[0096]) than the impurity concentration of the first low concentration region of each of the first connection portion (EP2a portion of SMb) and the second connection portion (EP2b portion of SMb).
Regarding claim 2, Yamamoto discloses the semiconductor device according to claim 1, wherein the first medium concentration region and the element portion 3 have the same impurity concentration as each other (Fig.29, para[0096]).
Regarding claim 3, Yamamoto discloses the semiconductor device according to claim 1, wherein a metal silicide layer (MS, para[0061]) is formed on a surface of each of the first semiconductor portion (EP2a) and the second semiconductor portion (EP2b).
Regarding claim 6, Yamamoto discloses the semiconductor device according to claim 1, further comprising an element isolation region (ST) formed in the substrate 1, penetrating through the semiconductor layer (SM) and the insulating layer (BX), and having a bottom portion (Fig.9) reaching the support substrate (SB), wherein the semiconductor layer (SM) located in the first region (1B) is surrounded by (Fig.1) the element isolation (ST) region in a plan view (Fig.1).
Regarding claim 8, Yamamoto discloses the semiconductor device according to claim 1, wherein the epitaxial semiconductor layer (EP) is formed also on the semiconductor layer (SM) located in the second region (1A), wherein the epitaxial semiconductor layer (EP) has: a third semiconductor portion (EP1a) formed on the semiconductor layer (SM) located in the second region (1A); and a fourth semiconductor portion (EP1b) formed on the semiconductor layer (SM) located in the second region (1A), and spaced apart from the third semiconductor portion (EP1a), wherein the MISFET 2 has a gate electrode GE formed on the semiconductor layer (SM) located in the second region 1A via a gate insulating film (GF), wherein a source region (SD) of the MISFET 2 is formed in the semiconductor layer SM and the third semiconductor portion (EP1a) located in the second region (1A), and wherein a drain region (SD) of the MISFET 2 is formed in the semiconductor layer (SM) and the fourth semiconductor portion (EP1b) located in the second region (1A).
Regarding claim 13, Yamamoto discloses the semiconductor device according to claim 8, wherein a thickness of the element portion (SM) is thinner (Fig.29) than a thickness of the gate electrode (GE).
Regarding claim 15, Yamamoto discloses the semiconductor device according to claim 1, wherein a gap (gap between EP2a and EP2b) is formed between the first semiconductor portion (EP2a) and the underlying semiconductor layer (SM) in a vicinity of an end of the first semiconductor portion (EP2a) on a side opposing the second semiconductor portion (EP2b).
Regarding claim 16, Yamamoto discloses the semiconductor device (Fig.29) according to claim 1, further comprising an interlayer insulating film (L1) formed on the substrate (1) so as to cover the semiconductor layer (SM) and the epitaxial semiconductor layer (EP), wherein a plurality of conductive plugs are embedded in the interlayer insulating film, and wherein the plurality of conductive plugs (PG) includes a first plug (PG) formed on the first semiconductor portion (EP2a) and electrically connected to the first semiconductor portion, and a second plug (PG) formed on the second semiconductor portion (EP2b) and electrically connected to the second semiconductor portion.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 103(a) Yamamoto US 2022/0157863 A1) in view of Botula et al ( US 2015/0236040 A1; Botula hereinafter).
Regarding claim 7, Yamamoto discloses the semiconductor device according to claim 6, wherein the semiconductor layer (SM) located in the first region (1B) and the semiconductor layer (SM) located in the second region (1A) are spaced apart (Fig.29) from each other by the element isolation region (ST) but fail to disclose wherein the semiconductor layer located in the second region is surrounded by the element isolation region in the plan view. However, Fig.2b, para[0017] of Botula discloses semiconductor layer 25 located in the first region (region of 25) is surrounded by the element isolation region 30 in a plan view. It would have been obvious to one having ordinary skill in the art to form the semiconductor layer surrounded by element isolation region in a plan view as shown by Botula for completely isolating the devices in the semiconductor layer.
Allowable Subject Matter
Claims 4-5, 9-12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-18 and 19 are allowed.
The following is an examiner’s statement of reasons for allowance:
The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device comprising: a second element portion located between the third connection portion and the fourth connection portion and, on which no epitaxial semiconductor layer is formed, wherein the first element portion is made of single crystal, wherein the second element portion is made of polycrystal, and wherein the first resistance element and the second resistance element are connected in series or in parallel in combination with all other limitations as recited in claim 17.
The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device comprising: the element portion has a single crystal region made of single crystal, and a polycrystalline region made of polycrystalline, and wherein the single crystal region and the polycrystalline region are connected in series between the first connection portion and the second connection portion in combination with all other limitations as recited in claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817