DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species C in the reply filed on 1 May 2026 is acknowledged. Claim 24 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1 May 2026.
After further consideration, the species restriction of 4 March 2026 is withdrawn as improperly defined according to the claimed invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 4 and 7 are rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claims 4 and 7 contain no further limitations beyond the claims upon which they depend. Claim 4 recites only operational condition of the apparatus in claims 1 and 3, without any further structural limitation of the apparatus. Claim 7 recites only operational condition of the apparatus in claims 1 and 6, without any further structural limitation of the apparatus. See MPEP 2114(II). Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-18 and 23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Fujiyama et al (US 20240371901 A1, hereinafter “Fujiyama”).
Applicant is reminded of MPEP 2114(I and II). The claims of the instant application are drawn to an apparatus. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. V. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). "Expressions relating the apparatus to contents thereof during an intended operation are of no significance in determining patentability of the apparatus claim." Ex parte Thibault, 164 USPQ 666, 667 (Bd. App. 1969).
Regarding Claim 1 - Fujiyama discloses a photoelectric conversion apparatus comprising: an output line (VSL [0130] and Fig. 6); and a plurality of unit pixels (PU [0181] and Fig. 6), wherein each of the plurality of unit pixels includes a photoelectric conversion element configured to generate signal electric charge based on incident light (PD [0100] and Fig. 6), and a plurality of transistors (TG, RST, SEL, FDG, AMP [0100] and Fig. 6), and wherein the plurality of transistors at least includes an amplifier transistor configured to have a gate into which the signal electric charge is input and to output a signal based on potential of the gate (AMP [0130] and Fig. 6), a selection transistor with which the amplifier transistor is connected to the output line (SEL [0131] and Fig. 6), and a reset transistor configured to reset the potential of the gate (RST [0128] and Fig. 6), the photoelectric conversion apparatus comprising: a first well on which the selection transistor is provided (P-well 26 in each pixel with SEL label [0112], [0123], and Fig. 7); and a second well on which at least two transistors in the plurality of transistors are provided (P-well 26 in each pixel with AMP, RST, and FDG labels each considered a second well [0112], [0123], and Fig. 7), wherein the first well is electrically separated from the second well (by the combination of 21 and 27 [0113] and Fig. 3).
PNG
media_image1.png
506
625
media_image1.png
Greyscale
PNG
media_image2.png
832
465
media_image2.png
Greyscale
Regarding Claim 2 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the first well is electrically separated from the second well with an insulating separator (Combination of 21 and 27 separates each well (active region) [0111-0112] and Fig. 3), and wherein the first well is surrounded by the insulating separator (Denoted by 21 in Fig. 2).
PNG
media_image3.png
509
720
media_image3.png
Greyscale
PNG
media_image4.png
411
399
media_image4.png
Greyscale
Regarding Claim 3 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the selection transistor is an N-type transistor ([0123]), and wherein potential of the first well during a period in which the selection transistor is in an on state is higher than potential of the first well during a period in which the selection transistor is in an off state (It is obvious the apparatus disclosed can be operated in the claimed manner, [0111] and Fig. 2, and this mode of operation does not differentiate the apparatus from the prior art. See MPEP 2114(II)).
Regarding Claim 4 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 3, wherein the potential of the first well during the period in which the selection transistor is in the on state is ground potential (It is obvious the apparatus disclosed can be operated in the claimed manner, [0111] and Fig. 2, and this mode of operation does not differentiate the apparatus from the prior art. See MPEP 2114(II)).
Regarding Claim 5 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the selection transistor is a P-type transistor ([0521]), and wherein the potential of the first well during a period in which the selection transistor is in an on state is lower than the potential of the first well during a period in which the selection transistor is in an off state (It is obvious the apparatus disclosed can be operated in the claimed manner, [0111] and Fig. 2, and this mode of operation does not differentiate the apparatus from the prior art. See MPEP 2114(II)).
Regarding Claim 6 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the selection transistor is an N-type transistor ([0123]), and wherein the potential of the first well during a period in which the selection transistor is in an off state is lower than the potential of the second well during the period (It is obvious the apparatus disclosed can be operated in the claimed manner, [0111] and Fig. 2, and this mode of operation does not differentiate the apparatus from the prior art. See MPEP 2114(II)).
Regarding Claim 7 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 6, wherein the potential of the second well during the period is ground potential (It is obvious the apparatus disclosed can be operated in the claimed manner, [0111] and Fig. 2, and this mode of operation does not differentiate the apparatus from the prior art. See MPEP 2114(II)).
Regarding Claim 8 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the selection transistor is an N-type transistor ([0123]), and wherein the potential of the first well during a period in which the selection transistor is in an on state is higher than the potential of the second well during the period (It is obvious the apparatus disclosed can be operated in the claimed manner, [0111] and Fig. 2, and this mode of operation does not differentiate the apparatus from the prior art. See MPEP 2114(II)).
Regarding Claim 9 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the selection transistor is a P-type transistor ([0521]), and wherein the potential of the first well during a period in which the selection transistor is in an on state is lower than the potential of the second well during the period (It is obvious the apparatus disclosed can be operated in the claimed manner, [0111] and Fig. 2, and this mode of operation does not differentiate the apparatus from the prior art. See MPEP 2114(II)).
Regarding Claim 10 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein a transistor that switches between connection and non-connection of capacitance to the gate of the amplifier transistor is provided on the second well as one of the at least two transistors in the plurality of transistors (FDG [0116] and Fig. 7).
Regarding Claim 11 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 10, wherein the amplifier transistor is provided on the second well as one of the at least two transistors in the plurality of transistors (AMP [0116] and Fig. 7).
Regarding Claim 12 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 10, wherein the reset transistor is provided on the second well as one of the at least two transistors in the plurality of transistors (RST [0116] and Fig. 7).
Regarding Claim 13 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 11, wherein the photoelectric conversion element is provided on the second well (PD [0112] and Figs. 2 and 3).
Regarding Claim 14 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 13, wherein the reset transistor is provided on the second well as one of the at least two transistors in the plurality of transistors (RST [0116] and Fig. 7).
Regarding Claim 15 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the amplifier transistor is provided on the second well as one of the at least two transistors in the plurality of transistors (AMP [0116] and Fig. 7).
Regarding Claim 16 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 15, wherein the reset transistor is provided on the second well as one of the at least two transistors in the plurality of transistors (RST [0116] and Fig. 7).
Regarding Claim 17 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 15, wherein the photoelectric conversion element is provided on the second well (PD [0112] and Figs. 2 and 3).
Regarding Claim 18 - Fujiyama further discloses the photoelectric conversion apparatus according to Claim 1, wherein the reset transistor is provided on the second well as one of the at least two transistors in the plurality of transistors (RST [0116] and Fig. 7).
Regarding Claim 23 - Fujiyama further discloses equipment including the photoelectric conversion apparatus according to Claim 1, the equipment further comprising at least one of: an optical apparatus corresponding to the photoelectric conversion apparatus (12031 [0506] and Fig. 64); a control apparatus configured to control the photoelectric conversion apparatus (12053 [0502] and Fig. 64); a processing apparatus configured to process a signal output from the photoelectric conversion apparatus (12051 [0508] and Fig. 64); a display apparatus configured to display information acquired by the photoelectric conversion apparatus (12062 [0511] and Fig. 64); a storage apparatus configured to store information acquired by the photoelectric conversion apparatus (Inside 12031, as 1004 for example [0485] and Fig. 62); and a mechanical apparatus configured to operate based on information acquired by the photoelectric conversion apparatus (12010 [0503] and Fig. 64).
PNG
media_image5.png
495
729
media_image5.png
Greyscale
PNG
media_image6.png
448
719
media_image6.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19, 21, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiyama et al (US 20240371901 A1, hereinafter “Fujiyama”), in view of Yokoyama (US 20230139176 A1, hereinafter “Yokoyama”).
Regarding Claim 19 - Fujiyama discloses all the limitations of claim 1.
Fujiyama fails to disclose the photoelectric conversion apparatus has a structure in which a first component is bonded to a second component, wherein the photoelectric conversion element is arranged in the first component, and wherein the first well and the second well are arranged in the second component.
However, Yokoyama discloses the photoelectric conversion apparatus has a structure in which a first component is bonded to a second component (100, and the combination of 200 and 300, Yokoyama [0153] and Fig. 26), wherein the photoelectric conversion element is arranged in the first component (100, Yokoyama [0153] and Fig. 26), and wherein the first well and the second well are arranged in the second component (The combination of 200 and 300, Yokoyama [0153] and Fig. 26).
Yokoyama discloses an analogous photoelectric conversion apparatus to Fujiyama. Yokoyama teaches stacking components containing photoelectric conversion elements, transistors and wells, and logic circuits to obtain a three-dimensional structure for the benefit of obtaining smaller imaging devices (Yokoyama [0002]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to stack components containing photoelectric conversion elements, transistors and wells, and logic circuits to obtain a three-dimensional structure for the benefit of obtaining smaller imaging devices.
Regarding Claim 21 - Fujiyama modified by Yokoyama discloses all the limitations of claim 19.
The combination of Fujiyama and Yokoyama further discloses the photoelectric conversion apparatus further includes a third component bonded to the second component (500, Yokoyama [0153] and Fig. 26), and wherein the third component includes a logic circuit that processes a pixel signal based on a signal electric charge output from each of the plurality of unit pixels ([0158]).
Regarding Claim 25 - Fujiyama discloses a semiconductor substrate in which a photoelectric conversion element that generates signal electric charge based on incident light is provided ([0486] and Fig. 62), the semiconductor substrate comprising: an output line (VSL [0130] and Fig. 6); and a plurality of transistors, wherein the plurality of transistors at least includes an amplifier transistor configured to have a gate into which the signal electric charge is input and to output a signal based on potential of the gate (AMP [0130] and Fig. 6), a selection transistor with which the amplifier transistor is connected to the output line (SEL [0131] and Fig. 6), and a reset transistor configured to reset the potential of the gate (RST [0128] and Fig. 6), the semiconductor substrate comprising: a first well on which the selection transistor is provided (P-well in each pixel with SEL label [0123] and Fig. 7); and a second well on which at least two transistors in the plurality of transistors are provided (P-well in each pixel with AMP, RST, and FDG labels [0123] and Fig. 7), wherein the first well is electrically separated from the second well (by the combination of 21 and 27 [0113] and Fig. 3).
Fujiyama fails to disclose the semiconductor substrate laminated on a component.
However, Yokoyama discloses the semiconductor substrate laminated on a component (The combination of 200 and 300 laminated on 100, Yokoyama [0153] and Fig. 26)).
Yokoyama discloses an analogous photoelectric conversion apparatus to Fujiyama. Yokoyama teaches stacking components containing photoelectric conversion elements, transistors and wells, and logic circuits to obtain a three-dimensional structure for the benefit of obtaining smaller imaging devices (Yokoyama [0002]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to stack components containing photoelectric conversion elements, transistors and wells, and logic circuits to obtain a three-dimensional structure for the benefit of obtaining smaller imaging devices.
Claims 20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiyama et al (US 20240371901 A1, hereinafter “Fujiyama”), in view of Yokoyama (US 20230139176 A1, hereinafter “Yokoyama”), and further in view of Ohura et al (US 20210399029 A1, hereinafter “Ohura”).
Regarding Claim 20 - Fujiyama modified by Yokoyama discloses all the limitations of claim 19.
The combination of Fujiyama and Yokoyama further discloses the second component includes a semiconductor substrate (20 and 30, Yokoyama [0068] and Fig. 26).
The combination of Fujiyama and Yokoyama fails to disclose the first component is electrically connected to the second component with a conductor that passes through an insulator that is provided from a first surface of the semiconductor substrate to a second surface opposed to the first surface.
However, Ohura discloses the first component is electrically connected to the second component with a conductor that passes through an insulator (e.g. 120E through 212, Ohura [0429] and Fig. 49) that is provided from a first surface of the semiconductor substrate to a second surface opposed to the first surface (From one side of 260S to the other, [0428] and Fig. 49).
Ohura discloses and analogous photoelectric conversion apparatus to Fujiyama. Ohura teaches a conductor that passes through an insulator that is provided from a first surface of the semiconductor substrate to a second surface opposed to the first surface for the benefit of connecting photodiodes to a pixel circuit that is facing away from the photodiodes (Ohura [0431]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include a conductor that passes through an insulator that is provided from a first surface of the semiconductor substrate to a second surface opposed to the first surface for the benefit of connecting photodiodes to a pixel circuit that is facing away from the photodiodes.
Regarding Claim 22 - Fujiyama modified by Yokoyama and Ohura discloses all the limitations of claim 20.
The combination of Fujiyama, Yokoyama, and Ohura further discloses the photoelectric conversion apparatus further includes a third component bonded to the second component (500, Yokoyama [0153] and Fig. 26), and wherein the third component includes a logic circuit that processes a pixel signal based on the signal electric charge output from each of the plurality of unit pixels ([0158]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights