DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding claim 1 objection, applicant amendment has been fully considered. The amendment overcomes the claim objection from the prior office action. Hence, the objection is withdrawn.
Regarding claims 1-10 rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections from the prior office action. Hence, 35 U.S.C. 112(b) rejection is withdrawn.
Applicant's arguments filed on 05/08/2026 have been fully considered but they are not persuasive.
First, Applicant’s argument that the first and second openings must be formed in the same physical trench is not commensurate with the scope of claim 1. Claim 1 recites a method comprising a trench, but does not preclude the semiconductor substrate from including a plurality of trenches. In fact, Applicant’s own disclosure illustrates two trenches 18 and 18’, as shown in Fig. 2A. Thus, claim 1 is not limited to an embodiment in which the first and second openings are formed in the same physical trench. Accordingly, Lee’s contact openings 115G and 115S satisfy the claimed first and second openings.
Second, Applicant’s argument concerning the “first etch process” is not commensurate with the scope of claim 1 as presently written. Claim 1 does not define what constitutes “a first etch process”. A process is not limited to a single step. Moreover, claim 1 does not require the first, second, and third openings to be formed simultaneously, by the same etching step, or using the same etchant. As set forth in the rejection, Lee teaches forming contact openings 155G and 155S to the gate conductor 115 and shield/filed-plate conductor 113. Lee further teaches, in Figs. 3F and 3G, etching steps that form the first and second openings and subsequently form the third opening. In particular, Lee teaches applying contact mask 160 and removing the LTO/BPSG layer 159 in the mesa regions, with the etch stopping at nitride stop layer 158. This removal of the overlying dielectric material forms a preliminary mesa-region opening corresponding to the claimed third opening.
The etching operations shown in Figs. 3F and 3G are commensurate with the claimed “first etch process” because the claim does not require the first etch process to be a single etching step. Rather, the claimed “first etch process” may include a plurality of etching steps that form the first, second, and third openings. Lee then teaches, further etching the exposed mesa-region opening to form opening 162 extending into the top surface epi layer grown on the semiconductor substrate 104. This later etching extends the depth of the previously formed third opening and corresponds to the claimed second etch process.
During the later mesa-deepening etch, Lee’s contact mask 160 protects the previously formed gate and shield/filed plater contact openings 155G and 155S while leaving the mesa-region opening exposed. Thus, Lee’s process is consistent with claim 1: the first etch process forms the first and second openings and a preliminary third opening through the overlying dielectric material, and the subsequent etch extends the third opening into the semiconductor substrate to form the mesa contact opening.
Applicant’s reliance on paragraph [0076] of the present application is also unpersuasive. The rejection does not require the gate and field-plate openings to remain exposed during the later mesa-deepening etch. Rather, consistent with Lee’s contact mask 160, those openings are protected while the mesa-region opening is exposed and deepened. Accordingly, Lee addresses the same over-etching concern identified by Applicant.
Therefore, Applicant’s arguments do not overcome the rejection of claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 7-9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170133473 A1).
Re: Independent Claim 1 (Currently amended), Lee discloses a method of fabricating contacts to a semiconductor substrate, the method comprising:
providing a semiconductor substrate (Fig. 3E, substrate 104) having a first major surface (Fig. 3E, top surface of substrate 104), a second major surface opposing the first major surface (Fig. 3E, opposite/lower surface of the same substrate 104), a trench formed in the first major surface and comprising a base and sidewalls (Fig. 3E and ¶ [0017], trench 110/120/130/140 that comprises base and sidewall etched into substrate 104), a gate electrode in the trench (Figs. 3D-3E, gate electrode 115), a field plate in the trench under the gate electrode (Figs. 3D-3E, shield electrode 113 under the gate electrode 115), electrically insulating material in the trench, the electrically insulating material electrically insulating the gate electrode and the field plate from the semiconductor substate and from each other (Fig. 2 and ¶ [0017], liner insulator 112 along trench sidewalls/bottom, gate oxide 116 and inter-poly dielectric 114 insulate gate electrode 115 and shield electrode (field plate) 113 from each other and from the semiconductor substrate 104), and a first electrically insulating layer arranged on the first major surface and on the trench (Fig. 3E and [0024], ONO stack including oxide 152, nitride stop 158 and, and LTO/BPSG 159 are arranged on the top surface of substrate 104 and on the trench ), wherein the base of the trench is positioned at a depth d from the first major surface, wherein 250 nm <=d<= 800 nm (depth of trench 110 is ranging from 0.6 to 1.5 μm, which includes embodiments with depth = 600nm – 800nm within the claimed range);
performing a first etch process to form:
a first opening that extends through the first electrically insulating layer and the electrically insulating material in the trench to the gate electrode (Figs. 3E-3F and ¶¶ [0027] - [0028], Lee applies a first contact mask and etches the ONO stack (159/158/152) to reach the gate electrode 115 in the transitional trench 130, thereby forming contact opening 115G to contact gate conductor 115);
a second opening that extends through the first electrically insulating layer and the electrically insulating material in the trench to the field plate (Figs. 3E-3F, ¶¶ [0027] - [0028], Lee etches the ONO stack (159/158/152) to reach the top conductive material 113 in the pickup trench 140, thereby forming contact opening 115S to contact shield/field-plate conductor 113), wherein the second opening is positioned at a portion of the trench in which the gate electrode is absent (Lee distinguishes that the ONO etch reaches conductive material 115 in the transition trench 130 and reaches conductive material 113 in the pickup trench 140, i.e., the field-plate contact opening 115S is formed at the pickup trench portion containing 113, rather than the gate-containing portion); and
a third opening that is positioned laterally adjacent the trench and that extends through the first electrically insulating layer to the first major surface of the semiconductor substrate (Fig. 3G, and [0027], Lee applies another contact mask 160 and performs an etch to open arrays of source/body contact openings in mesa regions 111 between gate trenches 110, beginning with removal of LTO/BPSG 159 and stopping at nitride stop 158. Although Lee doesn’t explicitly teach that the mesa-region window through the surface dielectric stack is formed as part of the same “first etch process” that forms 115S/115G, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Lee such that the mesa-region dielectric window is formed as part of the same overall dielectric-window opening stage as the gate/shield contact windows, because these are routine openings through the surface dielectric stack (159/158/152) and consolidating dielectric window formation yields predictable results);
applying a resist material that covers the first and second openings and leaves the third opening exposed (Lee teaches, in Fig 3G that, after forming contact openings 155G and 155S, another contact mask 160 is applied for the mesa/source-body opening etch that forms contact trenches 162; thus, during the Fig. 3G mesa etch, the mask/resist 160 leaves the mesa opening exposed to from 162 while covering/protecting the previously formed 155G/155S the mesa-region openings);
performing a second etch process to extend the depth of the third opening and form a mesa contact opening in the first major surface that extends into the semiconductor substrate (Lee teaches, in Fig. 3G and ¶ [0027] that the following breakthrough of nitride 158, contact trenches 162 are formed in the mesa regions, i.e., etched into substrate 104);
removing the resist material (Lee, in Fig. 3H and ¶ [0028], then proceeds to line barrier metal and deposit conductive material into the contact openings/trenches, which is performed after the masked etch step and thus implies the resist has been removed prior to barrier/plug formation); and
inserting conductive material into the first opening, the second opening, and the mesa contact opening and forming a gate contact, a field plate contact, and a mesa contact, respectively (Lee, in Fig. 3H and ¶ [0028], lines barrier metal on the sidewalls/bottom of contact openings 155S and 155G and contact trenches 162, then deposits conductive material (e.g., tungsten) to form conductive plugs 164, thus forming a gate contact, a filed plate contact, and a mesa contact respectively).
Re: Claim 5 (Original), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee further teaches
wherein an upper portion of the first electrically insulating layer is removed in the second etch process (Lee teaches, in Fig 3G and ¶ [0027], that the surface dielectric/insulating stack includes LTO layer 159 over nitride stop layer 158 over oxide 125, and during the mesa/contact etch sequence (performed under contact mask 160), the etching process starts with removal of the LTO layer 159 and stops at nitride stop layer 158. This teaches that an upper portion of the first electrically insulating layer (the upper LTO/BPSG portion 159) is removed during the etch process used to form/deepen the mesa opening).
Re: Claim 7 (Original), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee further teaches
wherein the inserting the conductive material comprises:
forming at least one barrier layer on the side walls and the base of each of the first opening, the second opening, and the mesa contact opening (Lee teaches, in ¶ [0028], that “a barrier metal (not shown in figure) is lined on the sidewalls and bottom of the contact openings 115S and 115G and contact trenches 162, where 115G/115S correspond to the first/second openings and 162 corresponds to the mesa contact opening) and on the upper surface of the first electrically insulating layer (Lee is silent as to expressly stating that the barrier metal is also formed on the upper surface of the first electrically insulating layer (e.g., the top of LTO/BPSG 159). Although Lee doesn’t teach barrier metal on that upper surface, it would have been obvious to a person of ordinary skill in the art that the barrier metal lining step would be implemented as a blanket/conformal deposition that necessarily also deposits on exposed upper dielectric surfaces around the openings (including the upper surface of 159) before any optional removal/planarization, because such barrier deposition processes are non-selective and yield predictable results); and
forming a conductive layer on the at least one barrier layer (Lee teaches, in ¶ [0028], “…followed by the deposition of a conductive material, e.g., tungsten, in the contact openings and contact trenches forming the conductive plugs 164”, i.e., conductive material on the barrier metal lining).
Re: Claim 8 (Original), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee further teaches
wherein the field plate has a length that is greater than the length of the gate electrode so that in at least one region of the trench, the field plate is uncovered by the gate electrode and the second opening is arranged in this region (In Fig. 3F, Lee teaches a device/trench arrangement in which a pickup trench 140 is provided and the pickup trench 140 contains first conductive material 113 (shield/filed-plate conductor). Lee further teaches the gate conductor 115 is provided in other trench locations (e.g., gate trenches and transition trench 130). Accordingly, this teaches that the field plate/shield conductor 113 extends into at least one trench region (pickup trench 140) where the gate conductor material 115 is absent, i.e., there is at least one region in which the filed plate is uncovered by the gate (and thus the field plate is effectively “longer” than gate electrode and Lee teaches that the “second opening” is 115S is arranged in this pickup trench region 140).
Re: Claim 9 (Original), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee further teaches
wherein the semiconductor substrate further comprises a drain region of a first conductivity type formed at the second surface, a drift region of the first conductivity formed on the drain region (Lee teaches, in Fig 3A and ¶ [0020] an N-type substrate 104 used as the drain of the device, and describes it as “an N+ silicon wafer with an N- epilayer grown on it, i.e., a first conductive type drain region (N+) at the opposing/backside major surface with an N- drift/epi region formed thereon), a body region of a second conductivity type that opposes the first conductivity type formed on the drift region (Lee teaches, in Fig. 3E and ¶ [0025], performing a body dopant implant followed by diffusion to form the body region 154. Because Lee is describing an N-type MOSFET, a person of ordinary skill in the art would understand the body region 154 is the opposite conductivity type (p-type for illustrated n-channel device)), and a source region of a first conductivity type formed on and/or in the body region (Lee teaches, in Fig. 3F and ¶ [0025], applying a source mask and performing a source dopant implant to form a plurality of source regions 156 in the active cell region 101), and wherein a base of the mesa contact opening is arranged in the body region (Lee teaches, in Fig. 3G and ¶ [0027], another contact mask 160 is applied and another etch process is performed to open the arrays of source and body contact openings in the mesa regions 111, and the contact trenches 162 are formed, i.e., the mesa contact opening corresponds to trench 162 formed as a source/body contact opening in the mesa. Accordingly, a “source and body contact opening” necessarily has its base arranged in (i.e., reaching/terminating at) the body region 154 (formed in Fig. 3E-3G) to provide the stated body contact).
Re: Claim 19 (New), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee further teaches
wherein after the first etching process, the second opening has the greatest depth from the first major surface of the semiconductor substrate, the first opening has a depth that is less than that of the second opening (Lee, fig. 3F, depth of second opening 115S is greater than depth of first opening 115G) and the third opening does not extend into the semiconductor substrate at all or has a depth from the first major surface that is less than that of the first opening (Lee teaches, in ¶ [0020], the substrate 104 comprises bulk substrate (silicon wafer) and epi layer grown on it. The depths of the openings would have been obvious processing parameter to optimize and clear ascertainable though routine experimentation and do not patentably distinguish applicant’s method from the know method of Lee. Obvious to try is a rationale that can support a conclusion of obviousness, i.e., choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. The Supreme Court in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) identified a number of rationales to support a conclusion of obviousness which are consistent with the proper "functional approach" to the determination of obviousness as laid down in Graham. In this case there are two identified predictable solution:
The third opening extends to the epi layer or
The third opening extends through the epi layer into the substrate (silicon wafer) 104.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to extend the third opening just into the epi layer thereby not extending it into the substrate 104.
Claim(s) 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170133473 A1) in view of Chou (US 20210407808 A1).
Re: Claim 2 (Original), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee is silent regarding
further comprising: before applying the resist material, forming a second electrically insulating layer on sidewalls and a base of each of the first, second and third openings and on an upper surface of the first electrically insulating layer.
However, Chou teaches the method further comprising: before applying the resist material, forming a second electrically insulating layer on sidewalls and a base of each of the first, second and third openings and on an upper surface of the first electrically insulating layer (Chou, in Fig. 2 and ¶ [0022], teaches conformally depositing a dielectric layer/liner 222 over the sidewalls and base of an opening 218, and further teaches that this dielectric layer 222 can be silicon nitride (electrically insulating).
Accordingly, although Lee doesn’t explicitly teach forming such a second electrically insulating liner in the already etched openings 155S/155G/162 and on the upper surface of 159 prior to applying mask 160, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chou’s conformal dielectric-liner step into Lee’s flow between (i) Lee’s formation of the openings through 159 and (ii) Lee’s application of contact mask 160, in order to improve isolation between the source/drain contact and an adjacent gate contact via to reduce leakage (Chou, ¶ [0010])).
Re: Claim 3 (Original), Lee and Chou disclose all the limitations of claim 2 on which this claim depends.
Chou further teaches
wherein during the second etch process, the second electrically insulating layer is removed from the upper surface of the first electrically insulating layer and from the base of the third opening and remains at least in part on the side walls of the third opening in the first electrically insulating layer (Chou teaches forming second electrically insulating layer as a dielectric liner 222 that is conformally deposited over surfaces of a contact opening 218. Chou further teaches, in Figs. 3 and 6 and ¶ [0023], that the liner can be recessed by an anisotropic etch such that (i) the liner 222 is removed from the bottom/base of the opening, (ii) the liner 222 is reduced/removed from upper surface, and (iii) the liner 222 remains along the sidewalls.
Accordingly, although Lee does not explicitly teach that, during Lee’s second etch process forming the mesa contact opening/ trench 162, a previously formed dielectric liner is removed from (a) the upper surface of Lee’s first insulating layer (e.g., 159) and (b) the base of the third opening while remaining on the sidewalls of the third opening through the first insulating layer, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to carry out Lee’s second etch process with the liner-recess step taught by Chou to expose the bottom of the mesa opening for continued silicon etch/contact formation while retaining sidewall insulation/protection in the dielectric portion of the opening).
Claim(s) 4, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170133473 A1) in view of Chou (US 20210407808 A1) further in view of Zang (US 20200335594 A1).
Re: Claim 4 (Original), Lee and Chou disclose all the limitations of claim 2 on which this claim depends.
Both Lee and Chou are silent regarding
further comprising: after removing the resist material, entirely removing the second electrically insulating layer.
However, Zang teaches further comprising: after removing the resist material, entirely removing the second electrically insulating layer (Zang teaches, in Fig. 10, that the dielectric liner 40 is removed from inside the opening 52, which exposes the underlying structure (e.g., gate structure 18), i.e., a teaching of complete removal of the liner from the opening rather than only horizontal-surface removal.
Although Lee does not explicitly teach an additional step of entirely removing the dielectric liner after resist removal (Lee proceeds from the masked etch to barrier/plug formation), it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to entirely remove the second electrically insulating layer (liner) after removing the resist and before conductive fill, as taught by Zang’s liner removal step, in order to ensure the contact openings are free of insulating material that could otherwise impede conductive fill or increase contact resistance (Zang, ¶ [0004]).
Re: Claim 6 (Currently amended), Lee and Chou disclose all the limitations of claim 2 on which this claim depends.
Chou further teaches
implanting dopants into the base of each of the first opening, the second opening, and the mesa contact opening (Lee is silent regarding implanting dopants into the bases of the already-formed contact openings (e.g., 115G/115S and the mesa opening to 162) after resist removal. Chou teaches, in Fig. 4 and ¶ [0024], an implantation directed down a contact opening to implant dopants into the bottom/base feature e.g., “the first implantation process 300 is directed to the source/drain feature 220 down the source/drain contact opening 218…”. Although Chou is silent regarding particular timing of the implantation within Lee’s flow, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee to include Chou’s implantation-through-an-opening step after resist removal and before final metallization/fill in order to dope the exposed base regions at the bottoms of the respective openings in order to provide a uniform dopant distribution on the exposed surface of the source/drain features (Chou, ¶ [0024]).
Lee and Chou are silent regarding
then entirely removing the second electrically insulating layer.
However, Zang teaches
then entirely removing the second electrically insulating layer (Zang teaches, in Fig. 10, that the dielectric liner 40 is removed from inside the opening 52, which exposes the underlying structure (e.g., gate structure 18), i.e., a teaching of complete removal of the liner from the opening rather than only horizontal-surface removal.
Although Lee in view of Chou does not explicitly teach an additional step of entirely removing the dielectric liner after resist removal (Lee proceeds from the masked etch to barrier/plug formation), it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to entirely remove the second electrically insulating layer (liner) after removing the resist and before conductive fill, as taught by Zang’s liner removal step, in order to ensure the contact openings are free of insulating material that could otherwise impede conductive fill or increase contact resistance (Zang, ¶ [0004]).
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20170133473 A1) in view of Bowers (US 20130234241 A1).
Re: Claim 10 (Original), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee further teaches
wherein the gate contact has a base positioned at a distance dg from the first major surface and 30 nm <=dg <= 200 nm (Lee teaches, in Fig. 3F and ¶ [0026], forming a gate contact to the gate conductor 115 via a gate contact opening (i.e., opening to gate conductor 115) formed through the ONO stack (152/158/159) to reach the top conductive material in the transitional trench 130, i.e., Gate-contact opening identified as 115G in Lee. Lee further teaches, in ¶ [0024], that the gate conductor (second conductive layer) 115 is etched back so that its upper surface is recessed about 100 Å-600 Å, e.g., about 300 Å below the surface of the substrate. Thus, the base of the gate contact (containing the recessed gate conductor is at about 300 Å= 30nm, which falls within 30-200nm),
Lee is silent regarding
wherein the field plate contact has a base positioned at a distance dfp from the first major surface and 300 nm <=dfp<= 500 nm, wherein the mesa contact has a base positioned at a distance dm from the first major surface and 80 nm <= dm <= 350 nm, and wherein dfp > dm > dg.
However, Bowers teaches
wherein the field plate contact has a base positioned at a distance dfp from the first major surface and 300 nm <=dfp<= 500 nm (Bowers teaches, in Figs. 2A and 2C and ¶ [0033], a trench structure in which a shield gate electrode 242 (field-plate/shield type electrode) is disposed below a flared rim 220, and the rim 200 extends over depth of about 0.2-0.5um; contacting the shield/field electrode below the rim inherently places the contact’s base at a depth on that order (e.g., 300nm – 500nm)), wherein the mesa contact has a base positioned at a distance dm from the first major surface and 80 nm <= dm <= 350 nm (Bowers teaches a self-aligned contact etch that removes silicon to a depth of about 0.3um (300nm) to expose contact surfaces (volume 282, contact surfaces 283), which is within the claimed range 80-350nm), and
wherein dfp > dm > dg (using the above teachings and obvious selections, dg ~30nm (Lee: ~ 30nm recess to gate conductor 115); dm~300nm (Bowers: ~ 300nm contact etch depth); dfp ~ 300-500nm (Bowers: ~200-500). So, the relationship dfp > dm > dg is satisfied)
Although Lee doesn’t explicitly teach this numeric ordering, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to adopt it to ensure the gate contact is shallowest (reducing risk of penetrating into underlying shield/ field structures), while the shield/field plate contact is deeper than the mesa contact, consistent with electrode placement and robust isolation/contact formation.
Re: Claim 20 (New), Lee discloses all the limitations of claim 1 on which this claim depends.
Lee is silent regarding
wherein after the second etching process, the first opening has a depth dg from the first major surface, the second opening has a depth dfp from the first major surface, the third opening has a depth dm from the first major surface, and dfp>dm> dg.
However, Bowers teaches
wherein after the second etching process, the first opening has a depth dg from the first major surface, the second opening has a depth dfp from the first major surface, the third opening has a depth dm from the first major surface, and dfp>dm> dg (although Lee teaches, in fig. 3F, depth of second opening 115S is greater than depth of first opening 115G, Lee is silent regarding the relation of depth of the third opening compared to the first and second opening. However, Bowers teaches, in Figs. 2A and 2C and ¶ [0033], a trench structure in which a shield gate electrode 242 (field-plate/shield type electrode) is disposed below a flared rim 220, and the rim 200 extends over depth of about 0.2-0.5um; contacting the shield/field electrode below the rim inherently places the contact’s base at a depth on that order (e.g., 300nm – 500nm). Bowers teaches a self-aligned contact etch that removes silicon to a depth of about 0.3um (300nm) to expose contact surfaces (volume 282, contact surfaces 283), which is within the range 80-350nm. Using the above teachings and obvious selections, dg ~30nm (Lee: ~ 30nm recess to gate conductor 115); dm~300nm (Bowers: ~ 300nm contact etch depth); dfp ~ 300-500nm (Bowers: ~200-500). So, the relationship dfp > dm > dg is satisfied).
Although Lee doesn’t explicitly teach this numeric ordering, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to adopt it to ensure the gate contact is shallowest (reducing risk of penetrating into underlying shield/ field structures), while the shield/field plate contact is deeper than the mesa contact, consistent with electrode placement and robust isolation/contact formation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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