DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on October 10, 2023 has been considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on November 21, 2023.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 15, 17, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “… closer to …” in claims 9, 15, 17, and 20 is a relative term which renders the claim indefinite. The term “… than …” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Regarding claims 9 and 17,
a first diffusion-preventing part that is closer to the device wafer
a sealing eutectic metal alloy layer that is closer to the cap wafer
a first conductive part that is closer to the device wafer
an interconnecting eutectic metal alloy layer that is closer to the cap wafer.
Regarding claims 15 and 20,
first standoff layer being closer to the device wafer
the second standoff layer being closer to the cap wafer
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-11, 13-14, 16-17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Miyatake (CN 102792168 A).
Claim 9, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) comprising:
a silicon device wafer (second substrate is a silicon device wafer, hereinafter, silicon device wafer 22, [0043], Fig. 1) that defines a device plane (device plane extends across the XY-plane) and a vertical direction that is perpendicular to the device plane (silicon device wafer 22 extends in the Z-direction, wherein the Z-direction is perpendicular to the XY-plane, [0043], Fig. 1), the device wafer 22 including MEMS device structures (device wafer 22 including MEMS device structures (i.e. anchoring part 37, movable part 38, spring part 39), hereinafter, MEMS device structures 37/38/39, [0043], Fig. 1); and
a cap wafer (first substrate 68 is similar to first substrate 21 which is a cap wafer, hereinafter, cap wafer 21/68, [0045] and [0062], Figs. 1 and 3) including an electrical circuit (cap wafer 21/68 includes an electrical circuit (i.e. first wiring layer 24 is electrically connected to fixed electrode layer 26 electrode pads 27, hereinafter, electrical circuit 24/26/27), [0049]; second wiring layer 25, hereinafter, electrical circuit 24/25/26/27 [0051], Fig. 1) and being attached to the silicon device wafer 22 by:
a vertical sealing structure (sealing joint 50 is a vertical sealing structure with insulating layer 23, frame part 40 and oxide insulating layer 35, hereinafter, vertical sealing structure 23/35/40/50, [0051], Fig. 1) that is substantially perpendicular to the device plane (vertical sealing structure 23/35/40/50 is substantially perpendicular to the XY-plane, [0051], Fig. 1) and surrounds the MEMS device structures 37/38/39 in the device plane (vertical sealing structure 23/35/40/50 surrounds the MEMS device structures 37/38/39 in the XY-plane, [0051], Fig. 1), so that the MEMS device structures 37/38/39 are disposed in at least one cavity (MEMS device structures 37/38/39 are enclosed by support substrate 36 and forms at least one cavity, hereinafter, at least one cavity S, [0042], Fig. 1; closed internal space S1, hereinafter, at least one cavity S/S1, [0063], Figs. 1 and 3) delimited at least by the device wafer 22, the cap wafer 21/68 and the sealing structure 23/35/40/50 (MEMS device structures 37/38/39 are disposed in at least one cavity S/S1 delimited at least by the device wafer 22, the cap wafer 21/68 and the sealing structure 23/35/40/50, [0043], Figs. 1 and 3), and
a vertical electrical connector (joint part 51 is a vertical electrical connection, hereinafter, vertical electrical connection 51, [0045] and [0051], Fig. 1) that connects the MEMS device structures 37/38/39 to the electrical circuit 24/25/26/27 (vertical electrical connection 51 connects MEMS device structures 37/38/39 to the electrical circuit 24/25/26/27 (i.e. second wiring layer 25), [0051], Fig. 1),
wherein the sealing structure 23/35/40/50 comprises at least a first diffusion-preventing part (oxide insulating layer 35 is a first diffusion-preventing part, hereinafter, first diffusion-preventing part 35, [0042], Figs. 1 and 3) that is closer to the device wafer 22 (first diffusion-preventing part 35 is closer to the device wafer 22, [0042], Figs. 1 and 3) and a sealing eutectic metal alloy layer (sealing structure 23/35/40/50 comprises a sealing joint 50 further comprising eutectic bonding between the first connecting metal layer 54 and second connecting metal layer 55, hereinafter, sealing eutectic metal alloy layer 54/55, [0056], Fig. 1) that is closer to the cap wafer 21/68 (sealing eutectic metal alloy layer 54/55 is closer to the cap wafer 21/68, [0056], Fig. 1), and
wherein the electrical connector 51 is connected to the electrical circuit 24/25/26/27 (vertical electrical connection 51 connects MEMS device structures 37/38/39 to the electrical circuit 24/25/26/27 (i.e. second wiring layer 25), [0051], Fig. 1) and comprises at least a first conductive part (Ti layer 52 is a first conductive part layer, hereinafter, first conductive part 52, [0055], Fig. 1) that is closer to the device wafer 22 (first conductive part 52 is closer to the device wafer 22, [0055], Fig. 1) and an interconnecting eutectic metal alloy layer (second wiring layer 25 is an interconnecting eutectic metal alloy layer, hereinafter, an interconnecting eutectic metal alloy layer 25, [0055], Figs. 1-2) that is closer to the cap wafer 21/68 (interconnecting eutectic metal alloy layer 25 is closer to the cap wafer 21/68, [0055], Fig. 1).
Claim 10, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 9, wherein the sealing structure 23/35/40/50 further comprises a second diffusion-preventing part (sealing structure 23/35/40/50 further comprises insulating layer 23, wherein insulating layer 23 is a second diffusion-preventing part, hereinafter, second diffusion-preventing part 23, [0045], Fig. 1) that lies between the sealing eutectic metallic alloy layer 54/55 and the cap wafer 21/68 (second diffusion-preventing part 23 lies between the sealing eutectic metallic alloy layer 54/55 and the cap wafer 21/68, [0045], Fig. 1).
Claim 11, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 10, wherein the electrical connector 51 further comprises a second conductive part (Ta layer 53 is a second conductive part, hereinafter, second conductive part 53, [0053], Figs. 1-2) that lies between the first conductive part 52 and the interconnecting eutectic metal alloy layer 54/55 (second conductive part 53 lies between the first conductive part 52 and the interconnecting eutectic metal alloy layer 54/55, [0053], Figs. 1-2).
Claim 13, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 9, wherein the first conductive part 52 is a part of the device wafer 22 (first conductive part 52 is a part of the device wafer 22, [0045], Figs. 1-2).
Claim 14, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 9, wherein the device wafer 22 is attached to the cap wafer 21/68 with one or more vertical standoffs 40/66 (device wafer 22 is attached to the cap wafer 21/68 with frame part 40, which are one or more vertical standoffs, hereinafter, one or more vertical standoffs 40, [0043], Fig. 1; protruding layer 66 is a one or more vertical standoffs, hereinafter, one or more vertical standoffs 40/66, [0063], Fig. 3).
Claim 16, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 14, wherein the first standoff layer 40/66 and the first diffusion-preventing layer 35 are a same material (first diffusion-preventing material 35 and first standoff material 40 are formed of a same material (i.e. silicon), [0042] and [0044], Fig. 1).
Claim 17, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) comprising:
a silicon device wafer (second substrate is a silicon device wafer, hereinafter, silicon device wafer 22, [0043], Fig. 1) having a planar surface (planar surface extends across the XY-plane) and including MEMS device structures (device wafer 22 including MEMS device structures (i.e. anchoring part 37, movable part 38, spring part 39), hereinafter, MEMS device structures 37/38/39, [0043], Fig. 1); and
a cap wafer (first substrate 68 is similar to first substrate 21 which is a cap wafer, hereinafter, cap wafer 21/68, [0045] and [0062], Figs. 1 and 3) including an electrical circuit (cap wafer 21/68 includes an electrical circuit (i.e. first wiring layer 24 is electrically connected to fixed electrode layer 26 electrode pads 27, hereinafter, electrical circuit 24/26/27), [0049]; second wiring layer 25, hereinafter, electrical circuit 24/25/26/27 [0051], Fig. 1) and being attached to the silicon device wafer 22 by:
a vertical sealing structure (sealing joint 50 is a vertical sealing structure with insulating layer 23, frame part 40 and oxide insulating layer 35, hereinafter, vertical sealing structure 23/35/40/50, [0051], Fig. 1) that is substantially perpendicular to the planar surface of the silicon device wafer 22 (vertical sealing structure 23/35/40/50 is substantially perpendicular to the XY-plane, [0051], Fig. 1) and that surrounds the MEMS device structures (vertical sealing structure 23/35/40/50 surrounds the MEMS device structures 37/38/39 in the XY-plane, [0051], Fig. 1) so that the MEMS device structures 37/38/39 are disposed in at least one cavity (MEMS device structures 37/38/39 are enclosed by support substrate 36 and forms at least one cavity, hereinafter, at least one cavity S, [0042], Fig. 1; closed internal space S1, hereinafter, at least one cavity S/S1, [0063], Figs. 1 and 3) delimited at least by the device wafer 22, the cap wafer 21/68 and the sealing structure 23/35/40/50 (MEMS device structures 37/38/39 are disposed in at least one cavity S/S1 delimited at least by the device wafer 22, the cap wafer 21/68 and the sealing structure 23/35/40/50, [0043], Figs. 1 and 3), and
a vertical electrical connector (joint part 51 is a vertical electrical connection, hereinafter, vertical electrical connection 51, [0045] and [0051], Fig. 1) that connects the MEMS device structures 37/38/39 to the electrical circuit 24/25/26/27 (vertical electrical connection 51 connects MEMS device structures 37/38/39 to the electrical circuit 24/25/26/27 (i.e. second wiring layer 25), [0051], Fig. 1),
wherein the sealing structure 23/35/40/50 comprises at least a first diffusion-preventing part (oxide insulating layer 35 is a first diffusion-preventing part, hereinafter, first diffusion-preventing part 35, [0042], Figs. 1 and 3) that is closer to the device wafer 22 (first diffusion-preventing part 35 is closer to the device wafer 22, [0042], Figs. 1 and 3) and a sealing eutectic metal alloy layer (sealing structure 23/35/40/50 comprises a sealing joint 50 further comprising eutectic bonding between the first connecting metal layer 54 and second connecting metal layer 55, hereinafter, sealing eutectic metal alloy layer 54/55, [0056], Fig. 1) that is closer to the cap wafer 21/68 (sealing eutectic metal alloy layer 54/55 is closer to the cap wafer 21/68, [0056], Fig. 1), and
wherein the electrical connector 51 is connected to the electrical circuit 24/25/26/27 (vertical electrical connection 51 connects MEMS device structures 37/38/39 to the electrical circuit 24/25/26/27 (i.e. second wiring layer 25), [0051], Fig. 1) and comprises at least a first conductive part (Ti layer 52 is a first conductive part layer, hereinafter, first conductive part 52, [0055], Fig. 1) that is closer to the device wafer 22 (first conductive part 52 is closer to the device wafer 22, [0055], Fig. 1) and an interconnecting eutectic metal alloy layer (second wiring layer 25 is an interconnecting eutectic metal alloy layer, hereinafter, an interconnecting eutectic metal alloy layer 25, [0055], Figs. 1-2) that is closer to the cap wafer 21/68 (interconnecting eutectic metal alloy layer 25 is closer to the cap wafer 21/68, [0055], Fig. 1).
Claim 19, Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 17, wherein the first conductive part 52 is a part of the device wafer 22 (first conductive part 52 is a part of the device wafer 22, [0045], Figs. 1-2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Miyatake (CN 102792168 A).
Claim 1, Miyatake discloses a method for sealing and contacting a microelectromechanical device (method for sealing and contacting a MEMS sensor 20 is a microelectromechanical device, hereinafter, microelectromechanical device 20, [0039], Fig. 1), the method comprising:
forming a first conductive part (second wiring layer 25 is a first conductive part, hereinafter, first conductive part 25, [0040], Fig. 1) in an interconnection region (width of first conductive part 25 and joint 51 forms an interconnection region, hereinafter, interconnection region 51, [0045], Fig. 1) of a device wafer (first substrate 21 is a device wafer, hereinafter, device wafer 21, [0045], Fig. 1) so that the first conductive part 25 is elevated above a main surface of the device wafer 21 (first conductive part 25 is elevated above a main surface of the device wafer 21 by insulating substrate layer 29, [0040], Fig. 1);
forming a layer of a first diffusion-preventing material (insulating layer 23 is a layer of a first diffusion-preventing material, hereinafter, layer of a first diffusion-preventing material 23, [0040], Fig. 1) on the device wafer 21 (layer of a first diffusion-preventing material 23 is formed on the device wafer 21, [0045], Fig. 1) and patterning the layer of the first diffusion-preventing material 23 to be present in a sealing region (sealing joint 50 is a sealing region, hereinafter, sealing region 50, [0045], Fig. 1) of the device wafer 21 (layer of a first diffusion-preventing material 23 is patterned to be present in a sealing region 50 of the device wafer 21, [0045], Fig. 1);
depositing a layer of a first eutectic metal alloy material (sealing joint 50 and joint 51 are further composed of a first connecting metal layer 54, hereinafter, first eutectic metal alloy material 54, [0053], Figs. 1-2) on the device wafer 21 (first eutectic metal alloy material 54 is deposited on the device wafer 21, [0053], Figs. 1-2) and patterning the layer of the first eutectic metal alloy material 54 to be present in the interconnection region 51 of the device wafer 21 on top of the first conductive part 25 (layer of the first eutectic metal alloy material 54 is present in the interconnection region 51 of the device wafer 21 on top of the first conductive part 25, [0053], Figs. 1-2) and in the sealing region 50 of the device wafer 21 on top of the first diffusion-preventing material 23 (layer of the first eutectic metal alloy material 54 is present in the sealing region 50 of the device wafer 21 on top of the first diffusion-preventing material 23, [0053], Figs. 1-2);
Miyatake does not explicitly disclose depositing a layer of a second eutectic metal alloy material on a cap wafer and patterning the layer of the second eutectic metal alloy material to be present in an interconnection region of the cap wafer and in a sealing region of the cap wafer; and bonding the cap wafer to the device wafer so that the interconnection region of the device wafer is aligned with the interconnection region of the cap wafer and the sealing region of the device wafer is aligned with the sealing region of the cap wafer.
However, Miyatake discloses depositing a layer of a second eutectic metal alloy material (sealing joint 50 and joint 51 are further composed of a second connecting metal layer 55, hereinafter, second eutectic metal alloy material 55, [0057], Figs. 1-2) on a cap wafer (first eutectic metal alloy material 54 and second eutectic metal alloy material 55 are deposited on a second substrate 67, hereinafter, cap wafer 67, [0063], Figs. 1-2) and patterning the layer of the second eutectic metal alloy material 55 to be present in an interconnection region 51 of the cap wafer 67 (Miyatake, second eutectic metal alloy material 55 to be present in an interconnection region 51 of the cap wafer 36 is patterned, Figs. 1 and 3) and in a sealing region 50 of the cap wafer 67 (second eutectic metal alloy material 55 to be present in a sealing region 50 of the cap wafer 67, [0063], Fig. 3); and
bonding the cap wafer 36/67 (support substrate 36 is similar to cap wafer 67, hereinafter, cap wafer 36/67, [0042], Figs. 1 and 3) to the device wafer 21/68 (first substrate 68 is similar to device wafer 21, hereinafter, device wafer 21/68, [0062], Figs. 1 and 3) so that the interconnection region 51 of the device wafer 21/68 is aligned with the interconnection region 51 of the cap wafer 36/67 (cap wafer 36/67 is bonded to the device wafer 21/68 such that the interconnection region 51 of the device wafer 21/68 is aligned with the interconnection region 51 of the cap wafer 36/67, [0063], Figs. 1 and 3) and the sealing region 50 of the device wafer 21/68 is aligned with the sealing region 50 of the cap wafer 36/67 (cap wafer 36/67 is bonded to the device wafer 21/68 such that the sealing region 50 of the device wafer 21/68 is aligned with the sealing region 50 of the cap wafer 36/67, [0063], Figs. 1 and 3). The combination to utilize features between embodiments of MEMS devices allows for the enclosure having improved bonding strength and airtightness at the eutectic bonding interface (Miyatake, [0017]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize features between embodiments of MEMS devices to allow for the enclosure having improved bonding strength and airtightness at the eutectic bonding interface (Miyatake, [0017]).
Claim 2, Miyatake discloses the method (method for sealing and contacting a MEMS sensor 20 is a microelectromechanical device 20, [0039], Fig. 1) according to claim 1, wherein, before the depositing of the layer of the second eutectic metal alloy material 55, the method further comprises:
forming a second conductive part (Ta layer 53 is a second conductive part, hereinafter, second conductive part 53, [0053], Figs. 1 and 3) in the interconnection region 51 of the cap wafer 36/67 (second conductive part 53 is formed in the interconnection region 51 of the cap wafer 36/67, [0053], Figs. 1-3); and
depositing a layer of a second diffusion-preventing material (oxide insulating layer 35 is a layer of a second diffusion-preventing material, hereinafter, layer of a second diffusion-preventing material 35, [0042], Figs. 1 and 3) on the cap wafer 36/67 (layer of a second diffusion-preventing material 35 is deposited on the cap wafer 36/67, [0042], Figs. 1 and 3) and patterning the layer of the second diffusion-preventing material 35 to be present at least in the sealing region 50 of the cap wafer 36/67 (layer of a second diffusion-preventing material 35 is patterned to be present at least in the sealing region 50 of the cap wafer 36/67, [0042], Figs. 1 and 3).
Claim 3, Miyatake discloses the method (method for sealing and contacting a MEMS sensor 20 is a microelectromechanical device 20, [0039], Fig. 1) according to claim 2, wherein the forming of the second conductive part 53 in the interconnection region 51 of the cap wafer 36/67 comprises depositing a layer of conductive material (forming of the second conductive part 53 in the interconnection region 51 of the cap wafer 36/67 comprises depositing a Ti layer 52 is a layer of conductive material, hereinafter, layer of conductive material 52, [0053], Figs. 1-3) on the cap wafer 36/67 and patterning the layer of the conductive material 52 to be present in the interconnection region 51 of the cap wafer 36/67 (layer of the conductive material 52 to be present in the interconnection region 51 of the cap wafer 36/67 is patterned).
Claim 5, Miyatake discloses the method (method for sealing and contacting a MEMS sensor 20 is a microelectromechanical device 20, [0039], Fig. 1) according to claim 1, wherein the first conductive part 25 is a part of the device wafer 21/68 (first conductive part 25 is a part of the device wafer 21/68, [0040], Figs. 1 and 3).
Claim 6, Miyatake discloses the method (method for sealing and contacting a MEMS sensor 20 is a microelectromechanical device 20, [0039], Fig. 1) according to claim 1, wherein each of the device wafer 21/68 and the cap wafer 36/67 comprise corresponding standoff regions (frame part 40 is a corresponding standoff region, hereinafter, corresponding standoff region 40, [0043], Fig. 1; protruding layer 66 is a corresponding standoff region, hereinafter, corresponding standoff region 40/66, [0063], Fig. 3).
Claim 7, Miyatake discloses the method (method for sealing and contacting a MEMS sensor 20 is a microelectromechanical device 20, [0039], Fig. 1) according to claim 6, wherein, before bonding the cap wafer 36/67 to the device wafer 21/68, the method further comprises:
depositing a layer of first standoff material (corresponding standoff region 40/66 includes a layer of a first standoff material 40/66 on the left-side of the MEMS device, hereinafter, layer of a first standoff material 40L/66L, [0063], Annotated Figs. 1 and 3) on the device wafer 21/68 and patterning the layer of the first standoff material 40L/66L to be present in the standoff region 40/66 of the device wafer 21/68 (layer of the first standoff material 40L/66L to be present in the standoff region 40/66 of the device wafer 21/68 is patterned, [0063], Annotated Figs. 1 and 3); and
depositing a layer of second standoff material (corresponding standoff region 40/66 includes a layer of a second standoff material 40/66 on the right-side of the MEMS device, hereinafter, layer of a second standoff material 40R/66R, [0063], Annotated Figs. 1 and 3) on the cap wafer 36/67 and patterning the layer of the second standoff material 40R/66R to be present in the standoff region 40/66 of the cap wafer 36/67 (layer of the second standoff material 40R/66R to be present in the standoff region 40/66 of the cap wafer 36/67 is patterned, Annotated Figs. 1 and 3).
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Annotated Fig. 1 (Miyatake) – Illustrates depositing a layer of a first standoff material 40L on the device wafer 21 and patterning the layer of the first standoff material 40L to be present in the standoff region 40 of the device wafer 21 and depositing a layer of second standoff material 40R on the cap wafer 36 and patterning the layer of the second standoff material 40R to be present in the standoff region 40 of the cap wafer 36.
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Annotated Fig. 3 (Miyatake) – Illustrates depositing a layer of a first standoff material 66L on the device wafer 68 and patterning the layer of the first standoff material 66L to be present in the standoff region 66 of the device wafer 68 and depositing a layer of second standoff material 66R on the cap wafer 67 and patterning the layer of the second standoff material 66R to be present in the standoff region 66 of the cap wafer 67.
Claim 8, Miyatake discloses the method (method for sealing and contacting a MEMS sensor 20 is a microelectromechanical device 20, [0039], Fig. 1) according to claim 7, wherein the first standoff material 40 (i.e. silicon on insulator) and the first diffusion-preventing material 23 are a same material (first diffusion-preventing material 23 and first standoff material 40 are formed of a same material (i.e. silicon), [0042], Fig. 1).
Allowable Subject Matter
Claims 4, 12, 15, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Miyatake (CN 102792168 A), fails to disclose the following limitations in combination with the rest of the claim.
Regarding claim 4, wherein the conductive material and the second-diffusion-preventing material are a same material.
Miyatake does not disclose the following limitation; wherein the conductive material and the second-diffusion-preventing material are a same material.
Regarding claim 12, wherein the second diffusion-preventing part and the second conductive part are a same material.
Miyatake does not disclose the following limitation; wherein the second diffusion-preventing part and the second conductive part are a same material.
Regarding claim 15, wherein each of the one or more vertical standoffs comprises a first standoff layer and a second standoff layer, with the first standoff layer being closer to the device wafer and the second standoff layer being closer to the cap wafer.
Miyatake does not disclose the following limitations; wherein each of the one or more vertical standoffs comprises a first standoff layer and a second standoff layer, with the first standoff layer being closer to the device wafer and the second standoff layer being closer to the cap wafer.
Regarding claim 18, wherein the second diffusion-preventing part and the second conductive part are a same material.
Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 17, wherein the sealing structure 23/35/40/50 further comprises a second diffusion-preventing part (sealing structure 23/35/40/50 further comprises insulating layer 23, wherein insulating layer 23 is a second diffusion-preventing part, hereinafter, second diffusion-preventing part 23, [0045], Fig. 1) that lies between the sealing eutectic metallic alloy layer 54/55 and the cap wafer 21/68 (second diffusion-preventing part 23 lies between the sealing eutectic metallic alloy layer 54/55 and the cap wafer 21/68, [0045], Fig. 1), wherein the electrical connector 51 further comprises a second conductive part (Ta layer 53 is a second conductive part, hereinafter, second conductive part 53, [0053], Figs. 1-2) that lies between the first conductive part 52 and the interconnecting eutectic metal alloy layer 54/55 (second conductive part 53 lies between the first conductive part 52 and the interconnecting eutectic metal alloy layer 54/55, [0053], Figs. 1-2).
Miyatake does not disclose the following limitation; wherein the second diffusion-preventing part and the second conductive part are a same material.
Regarding claim 20, wherein each of the one or more vertical standoffs comprises a first standoff layer and a second standoff layer, with the first standoff layer being closer to the device wafer and the second standoff layer being closer to the cap wafer.
Miyatake discloses a microelectromechanical device (microelectromechanical device 20, [0039], Fig. 1) according to claim 17, wherein the device wafer 22 is attached to the cap wafer 21/68 with one or more vertical standoffs 40/66 (device wafer 22 is attached to the cap wafer 21/68 with frame part 40, which are one or more vertical standoffs, hereinafter, one or more vertical standoffs 40, [0043], Fig. 1; protruding layer 66 is a one or more vertical standoffs, hereinafter, one or more vertical standoffs 40/66, [0063], Fig. 3).
Miyatake does not disclose the following limitations; wherein each of the one or more vertical standoffs comprises a first standoff layer and a second standoff layer, with the first standoff layer being closer to the device wafer and the second standoff layer being closer to the cap wafer.
Conclusion
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812