Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 10/10/2023 and 1/31/2024, U.S. patents and Foreign Patents have been considered.
Election/Restrictions
Applicant’s election with traverse of Group I (claims 1-20) in the reply filed on 12/09/2025 is acknowledged. The traversal is on the ground(s) that the restriction creates no unreasonable search burden because a search of Group I would yield prior art equally applicable to Group II, as both groups share the same inventive concept and technical subject matter. This is not found persuasive because Group I (method/CRM claims) and Group II (product claims) are patentably distinct under 35 U.S.C. 121 — the product can exist without being made by the method, and a search for the structural features of the packaging circuitry (connection vias, RDLs, interposer arrangement) requires a materially different search from the process steps (comparing via positions, generating position data, projecting mask patterns). Overlap in subject matter does not eliminate the distinct search burden. The requirement is still deemed proper and is therefore made FINAL.
Claims 21-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/09/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Scanlan et al. (United States Patent Application Publication US20130280826A1), hereinafter referenced as Scanlan.
In regards to claim 1, (Scanlan) shows a method, comprising:
comparing positions of vias and via locations; Scanlan [0063, 0065] teaches that design software measures actual positions of dies after molding and compares those positions against expected design-file positions to determine positional offsets in x, y, and orientation, teaching comparing positions of vias and via locations.
generating position data based on the comparing the positions of vias and the via locations; Scanlan [0063] and [0081] teach that design software generates a pattern design file based on the measured die positions and calculated offsets, the generated file constituting position data generated based on the comparing the positions of vias and the via locations.
providing the position data of the vias to a digital lithography device; Scanlan [0081] and [0100] teach that the pattern design file is imported by the maskless patterning machine 172, thereby providing the position data of the vias to a digital lithography device.
updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias; Scanlan [0063] teaches that design software adjusts the RDL pattern design to correspond to the actual measured die positions so that patterned RDL traces align with the actual via positions, teaching updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias.
projecting the RDL mask pattern with the digital lithography device; Scanlan [0063] and [0100] teach that the maskless patterning machine 172 uses the imported adaptive design file to project the RDL mask pattern onto the panelized packaging substrate, teaching projecting the RDL mask pattern with the digital lithography device.
In regards to claim 2, (Scanlan) shows the method of claim 1:
wherein a metrology device determines the positions of vias; Scanlan [0063] teaches that a measurement system determines the actual positions of dies on the panelized substrate for use in the comparison step, teaching a metrology device that determines the positions of vias.
In regards to claim 4, (Scanlan) shows the method of claim 1:
wherein the position data includes x-shifts and y-shifts of the vias; Scanlan [0063] teaches that the positional offsets include x, y, and orientation components for each die, teaching position data that includes x-shifts and y-shifts of the vias.
In regards to claim 6, (Scanlan) shows the method of claim 1:
wherein a processing unit of the digital lithography device is a pattern generator; Scanlan [0081] and [0100] teach that the patterning machine 172 is a maskless lithography system that directly generates patterned exposures from the imported adaptive design files, teaching a processing unit of the digital lithography device that is a pattern generator.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US20130280826A1 (Scanlan) in view of US20230288822A1 (Mueller).
In regards to claim 3, (Scanlan) does not show: wherein an interface of the digital lithography device receives the position data;
Mueller teaches wherein an interface of the digital lithography device receives the position data; Mueller [0057] teaches that controller 660, the controller of the digital lithography station itself, receives the modified UMF position data file from the upstream controller, teaching an interface of the digital lithography device that receives the position data.
The motivation to combine Scanlan and Mueller is that both references are directed to adaptive semiconductor packaging patterning using digital lithography with die-position feedback. A person of ordinary skill in the art would combine Mueller’s explicit lithography-controller-level position-data reception into Scanlan’s adaptive patterning framework with a reasonable expectation of success.
In regards to claim 5, (Scanlan) does not show: wherein an interface of the digital lithography device at least one of optimizes, verifies, or updates a design file;
Mueller teaches wherein an interface of the digital lithography device at least one of optimizes, verifies, or updates a design file; Mueller [0057] and [0065] teach that controller 660 of the digital lithography station receives the position data file and generates or adjusts the virtual mask layout accordingly, teaching an interface of the digital lithography device that at least one of optimizes, verifies, or updates a design file.
The motivation to combine Scanlan and Mueller is the same as that set forth above with respect to claim 3. A person of ordinary skill in the art would combine Mueller’s controller-level design-file update functionality into Scanlan’s adaptive patterning framework with a reasonable expectation of success.
Claims 7–20 are rejected under 35 U.S.C. 103 as being unpatentable over US20130280826A1 (Scanlan) in view of US20220293576A1 (Wang).
In regards to claim 7, (Scanlan) shows a method, comprising:
comparing positions of vias and via locations; Scanlan [0063] teaches that design software measures actual positions of dies after molding and compares those positions against expected design-file positions to determine positional offsets in x, y, and orientation, teaching comparing positions of vias and via locations.
generating position data based on the comparing the positions of vias and the via locations; Scanlan [0063] and [0081] teach that design software generates a pattern design file based on the measured die positions and calculated offsets, the generated file constituting position data generated based on the comparing the positions of vias and the via locations.
providing the position data of the vias to a digital lithography device; Scanlan [0081] and [0100] teach that the pattern design file is imported by the maskless patterning machine 172, thereby providing the position data of the vias to a digital lithography device.
projecting the RDL mask pattern with the digital lithography device, the RDLs contacting the second endpoint of the connection vias; Scanlan [0063] and [0100] teach that the maskless patterning machine 172 uses the imported adaptive design file to project the RDL mask pattern onto the packaging substrate, teaching projecting the RDL mask pattern with the digital lithography device.
(Scanlan) differs from the claimed invention in that it does not explicitly disclose generating a connection via mask pattern according to the position data, the connection via mask pattern includes connection vias having a first endpoint to contact the vias and a second endpoint to contact redistributed metal layer (RDLs) to be patterned at the via locations according to a RDL mask pattern; and projecting the connection via mask pattern with the digital lithography device, the connection vias having the first endpoint to contacting the vias.
Wang teaches generating a connection via mask pattern according to the position data, the connection via mask pattern includes connection vias having a first endpoint to contact the vias and a second endpoint to contact redistributed metal layer (RDLs) to be patterned at the via locations according to a RDL mask pattern; Wang [0170], [0177], and [0213] teach that a post-alignment process generates a graphic file for a terminal expansion layer including expansion wires connecting chip terminals through via holes—with a first endpoint contacting the terminals/vias—to redistribution layers—with a second endpoint contacting the RDLs—wherein the file is generated based on identified actual terminal positions, teaching generating a connection via mask pattern according to the position data wherein connection vias have a first endpoint to contact the vias and a second endpoint to contact redistributed metal layer (RDLs).
Wang teaches projecting the connection via mask pattern with the digital lithography device, the connection vias having the first endpoint to contacting the vias; Wang [0170] and [0213] teach that the digital exposure machine projects the terminal expansion layer wiring pattern using maskless lithography, with the expansion wire via holes contacting the chip terminals at their first endpoint, teaching projecting the connection via mask pattern with the digital lithography device, the connection vias having the first endpoint to contacting the vias.
The motivation to combine Scanlan and Wang is that both references are directed to post-alignment digital lithography for semiconductor packaging interconnects. A person of ordinary skill in the art would incorporate Wang’s connection-via intermediate layer approach into Scanlan’s adaptive IC packaging framework to bridge positionally shifted vias to fixed RDL locations, with a reasonable expectation of success.
In regards to claim 8, (Scanlan) shows the method of claim 7:
wherein a metrology device determines at the positions and generates the position data; Scanlan [0063] teaches that a measurement system determines actual die positions on the panelized substrate and generates the resulting pattern design file, teaching a metrology device that determines at the positions and generates the position data.
In regards to claim 9, (Scanlan) does not show: wherein an interface of the digital lithography device receives the position data from the metrology device;
Wang teaches wherein an interface of the digital lithography device receives the position data from the metrology device; Wang [0130] teaches that coordinate information from the position determination step is converted into a file recognized and received by the digital exposure machine, teaching an interface of the digital lithography device that receives the position data from the metrology device.
The motivation to combine Scanlan and Wang is that both references are directed to post-alignment digital lithography for semiconductor packaging interconnects. A person of ordinary skill in the art would incorporate Wang’s connection-via intermediate layer approach into Scanlan’s adaptive IC packaging framework to bridge positionally shifted vias to fixed RDL locations, with a reasonable expectation of success.
In regards to claim 10, (Scanlan) shows the method of claim 7:
wherein the position data includes x-shifts and y-shifts of the vias; Scanlan [0063] teaches that the positional offsets include x, y, and orientation components for each die, teaching position data that includes x-shifts and y-shifts of the vias.
In regards to claim 11, (Scanlan) does not show: wherein an interface of the digital lithography device at least one of optimizes, verifies, or updates a design file;
Wang teaches wherein an interface of the digital lithography device at least one of optimizes, verifies, or updates a design file; Wang [0174] teaches that an automatic wiring file is generated from recognition and analysis results and provided to the digital exposure machine for patterning, teaching an interface of the digital lithography device that at least one of optimizes, verifies, or updates a design file.
The motivation to combine Scanlan and Wang is that both references are directed to post-alignment digital lithography for semiconductor packaging interconnects. A person of ordinary skill in the art would incorporate Wang’s connection-via intermediate layer approach into Scanlan’s adaptive IC packaging framework to bridge positionally shifted vias to fixed RDL locations, with a reasonable expectation of success.
In regards to claim 12, (Scanlan) shows the method of claim 7:
wherein a processing unit of the digital lithography device is a pattern generator; Scanlan [0081] and [0100] teach that the patterning machine 172 is a maskless lithography system that directly generates patterned exposures from the imported adaptive design files, teaching a processing unit of the digital lithography device that is a pattern generator.
In regards to claim 13, (Scanlan) shows the method of claim 7:
wherein the vias of disposed over interposers; Scanlan [0063] teaches a die-last panelized IC packaging process in which vias are formed over packaging substrates serving as the interconnect base layer, teaching the vias of disposed over interposers.
In regards to claim 14, (Scanlan) shows the method of claim 13:
wherein dies are to be attached the interposers; Scanlan [0063] teaches that dies are embedded and attached to the packaging substrate in a die-last advanced packaging process, teaching dies are to be attached the interposers.
In regards to claim 15, (Scanlan) shows a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause a computer system to perform the steps of:
comparing positions of vias and via locations; Scanlan [0063] teaches that design software measures actual positions of dies after molding and compares those positions against expected design-file positions to determine positional offsets in x, y, and orientation, teaching comparing positions of vias and via locations.
generating position data based on the comparing the positions of vias and the via locations; Scanlan [0063] and [0081] teach that design software generates a pattern design file based on the measured die positions and calculated offsets, the generated file constituting position data generated based on the comparing the positions of vias and the via locations.
providing the position data of the vias to a digital lithography device; Scanlan [0081] and [0100] teach that the pattern design file is imported by the maskless patterning machine 172, thereby providing the position data of the vias to a digital lithography device.
projecting the RDL mask pattern with the digital lithography device, the RDLs contacting the second endpoint of the connection vias; Scanlan [0063] and [0100] teach that the maskless patterning machine 172 uses the imported adaptive design file to project the RDL mask pattern onto the packaging substrate, teaching projecting the RDL mask pattern with the digital lithography device.
(Scanlan) differs from the claimed invention in that it does not explicitly disclose generating a connection via mask pattern according to the position data, the connection via mask pattern includes connection vias having a first endpoint to contact the vias and a second endpoint to contact redistributed metal layer (RDLs) to be patterned at the via locations according to a RDL mask pattern; and projecting the connection via mask pattern with the digital lithography device, the connection vias having the first endpoint to contacting the vias.
Wang teaches generating a connection via mask pattern according to the position data, the connection via mask pattern includes connection vias having a first endpoint to contact the vias and a second endpoint to contact redistributed metal layer (RDLs) to be patterned at the via locations according to a RDL mask pattern; Wang [0170], [0177], and [0213] teach that a post-alignment process generates a graphic file for a terminal expansion layer including expansion wires connecting chip terminals through via holes—with a first endpoint contacting the terminals/vias—to redistribution layers—with a second endpoint contacting the RDLs—wherein the file is generated based on identified actual terminal positions, teaching generating a connection via mask pattern according to the position data wherein connection vias have a first endpoint to contact the vias and a second endpoint to contact redistributed metal layer (RDLs).
Wang teaches projecting the connection via mask pattern with the digital lithography device, the connection vias having the first endpoint to contacting the vias; Wang [0170] and [0213] teach that the digital exposure machine projects the terminal expansion layer wiring pattern using maskless lithography, with the expansion wire via holes contacting the chip terminals at their first endpoint, teaching projecting the connection via mask pattern with the digital lithography device, the connection vias having the first endpoint to contacting the vias.
The motivation to combine Scanlan and Wang is that both references are directed to post-alignment digital lithography for semiconductor packaging interconnects. A person of ordinary skill in the art would incorporate Wang’s connection-via intermediate layer approach into Scanlan’s adaptive IC packaging framework to bridge positionally shifted vias to fixed RDL locations, with a reasonable expectation of success.
In regards to claim 16, (Scanlan) shows the non-transitory computer-readable medium of claim 15:
wherein a metrology device determines at the positions and generates the position data; Scanlan [0063] teaches that a measurement system determines actual die positions on the panelized substrate and generates the resulting pattern design file, teaching a metrology device that determines at the positions and generates the position data.
In regards to claim 17, (Scanlan) does not show: wherein an interface of the digital lithography device receives the position data from the metrology device;
Wang teaches wherein an interface of the digital lithography device receives the position data from the metrology device; Wang [0130] teaches that coordinate information from the position determination step is converted into a file recognized and received by the digital exposure machine, teaching an interface of the digital lithography device that receives the position data from the metrology device.
The motivation to combine Scanlan and Wang is that both references are directed to post-alignment digital lithography for semiconductor packaging interconnects. A person of ordinary skill in the art would incorporate Wang’s connection-via intermediate layer approach into Scanlan’s adaptive IC packaging framework to bridge positionally shifted vias to fixed RDL locations, with a reasonable expectation of success.
In regards to claim 18, (Scanlan) shows the non-transitory computer-readable medium of claim 15:
wherein the position data includes x-shifts and y-shifts of the vias; Scanlan [0063] teaches that the positional offsets include x, y, and orientation components for each die, teaching position data that includes x-shifts and y-shifts of the vias.
In regards to claim 19, (Scanlan) does not show: wherein an interface of the digital lithography device at least one of optimizes, verifies, or updates a design file;
Wang teaches wherein an interface of the digital lithography device at least one of optimizes, verifies, or updates a design file; Wang [0174] teaches that an automatic wiring file is generated from recognition and analysis results and provided to the digital exposure machine for patterning, teaching an interface of the digital lithography device that at least one of optimizes, verifies, or updates a design file.
The motivation to combine Scanlan and Wang is that both references are directed to post-alignment digital lithography for semiconductor packaging interconnects. A person of ordinary skill in the art would incorporate Wang’s connection-via intermediate layer approach into Scanlan’s adaptive IC packaging framework to bridge positionally shifted vias to fixed RDL locations, with a reasonable expectation of success.
In regards to claim 20, (Scanlan) shows the non-transitory computer-readable medium of claim 15:
wherein a processing unit of the digital lithography device is a pattern generator; Scanlan [0081] and [0100] teach that the patterning machine 172 is a maskless lithography system that directly generates patterned exposures from the imported adaptive design files, teaching a processing unit of the digital lithography device that is a pattern generator.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851