Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0202458 A1 Jung et al (herein “Jung”).
Regarding Claim 1, Jung discloses:
A semiconductor structure (#1, see generally the generic embodiment shown in Fig. 3 and view of memory cell shown in Fig. 4, reference may be made to other embodiments when specified), comprising:
an alternating stack of insulating layers (#120b) and electrically conductive layers (#150, comprising elements #152, #154, #156) that is located on a front side (bottom side with respect to Fig. 3) of at least one semiconductor material layer (#177a, [0044]);
memory openings (Fig. 4, #130) vertically extending through the alternating stack (#120b, #150); memory opening fill structures (shown in Fig. 4, includes elements that lie within width #W1) located in the memory openings (#130) and comprising a respective vertical semiconductor channel (#136) and a respective vertical stack of memory elements (#134b, [0076]);
a dielectric material portion (#120c) laterally offset from the alternating stack (#120b, #150);
a connection via structure (#166a) vertically extending through the dielectric material portion (#120c);
a metallic plate (#177b) in contact with a proximal end surface of the connection via structure (#166a); and
a backside contact pad (#179b) in electrical contact with the metallic plate (#177b) and spaced from the connection via structure (#166a) by the metallic plate (#177b).
Regarding Claim 2, Jung discloses: The semiconductor structure of Claim 1,
wherein the metallic plate (#179b) has a planar horizontal surface (see annotated Fig. 3 below) within a first horizontal plane (see annotated Fig. 3 below) including a bottommost surface of the at least one semiconductor material layer (#177a); and
the connection via structure has a variable horizontal cross-sectional area that increases with a vertical distance from the first horizontal plane (see tapered contact plug #166a in Fig. 3).
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Jung Fig. 3 – Annotated by Examiner
Regarding Claim 3, Jung discloses: The semiconductor structure of Claim 2,
wherein the planar horizontal surface (see annotated Fig. 3 above) of the metallic plate (#177b) comprises a horizontal top surface of the metallic plate (#177b).
Regarding Claim 4, Jung discloses: The semiconductor structure of Claim 2,
wherein the planar horizontal surface (see annotated Fig. 3 above) of the metallic plate (#177b) comprises a horizontal bottom surface of the metallic plate (#177b).
Regarding Claim 5, Jung discloses: The semiconductor structure of Claim 2,
further comprising a buffer dielectric layer (#185) contacting a bottom surface of the metallic plate (#177b).
Note, the buffer dielectric layer #185 contacts/surrounds the border of the bottom surface of the metallic plate in Fig. 3, therefore under the broadest reasonable interpretation the buffer dielectric layer contacts a portion of the bottom surface of the metallic plate.
Regarding Claim 6, Jung discloses: The semiconductor structure of Claim 5,
further comprising a metallic source structure (#179a) contacting the bottommost surface of the at least one semiconductor material layer (#177a) and having a same material composition ([0045]) and a same thickness (see Fig. 3, [0045]) as the metallic plate (#177b), wherein a bottom surface of the metallic source structure contacts the buffer dielectric layer.
Note, the buffer dielectric layer #185 contacts/surrounds the border of the bottom surface of the metallic source structure in Fig. 3, therefore under the broadest reasonable interpretation the buffer dielectric layer contacts a portion of the bottom surface of the metallic source structure.
Regarding Claim 7, Jung discloses: The semiconductor structure of Claim 6,
wherein the metallic source structure (#177a) and the metallic plate (#177b) are embedded in the buffer dielectric layer (#185), and sidewalls of the metallic plate (#177b) contact the buffer dielectric layer (#185).
Regarding Claim 10, Jung discloses: The semiconductor structure of Claim 5,
wherein the buffer dielectric layer (#185) contacts the bottommost surface of the at least one semiconductor material layer (#177a), and sidewalls of the metallic plate (#177b) contacts the buffer dielectric layer (#185) or the dielectric material portion (#120c).
Note, the buffer dielectric layer #185 contacts/surrounds the border of the bottom surface of the at least one semiconductor layer in Fig. 3, therefore under the broadest reasonable interpretation the buffer dielectric layer contacts a portion of the bottom surface of the metallic plate.
Claim 16 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0093629 A1 Kim et al (herein “Kim”).
Regarding Claim 16, Kim discloses:
A method of forming a semiconductor structure (see generally the embodiment shown in Fig. 7, memory structure cross section in Fig. 14, and corresponding methods of manufacturing shown in Figs. 27A-33A and described in [0125]-[0159]), comprising:
forming a buffer dielectric layer (#101, Fig. 27A) over a first substrate (#10);
forming a metallic plate (pad portion of #LP3) over the buffer dielectric layer (#101) in a contact region (#CNR1, #CNR2);
forming at least one semiconductor material layer (#SC, #SP, [0064]-[0066]) over the buffer dielectric layer (#101) in a memory array region (#CAR);
forming an alternating stack of insulating layers (#ILD, Fig. 30A, [0145]) and spacer material layers (#SL, Fig. 30A, [0145]) over the at least one semiconductor material layer (#SC, #SP), wherein the spacer material layers (#SL) are formed as, or are subsequently replaced with, electrically conductive layers (#GE, Fig. 31A, [0156]);
forming a dielectric material portion (#120) over the metallic plate (#LP3);
forming memory openings (opening not explicitly listed, see vertical structure VS in Fig. 3) through the alternating stack (#ILD, GE);
forming memory opening fill structures (#VP, #DSP, [0073]-[0077]) in the memory openings (#VS), wherein each of the memory opening fill structures (#VP) comprises a respective vertical semiconductor channel (#VP) and a respective vertical stack of memory elements (#DSP);
forming a connection via structure (#TP3) through the dielectric material portion (#120) directly on a top surface of the metallic plate (#LP3); and
forming a backside contact pad (#PLP) directly on a backside surface of the metallic plate (#PLP).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0202458 A1 Jung et al in view of US 2020/0266146 A1 Nishida et al (herein “Nishida”).
Regarding Claim 8, Jung discloses: The semiconductor structure of Claim 6,
Jung does not explicitly disclose:
wherein the sidewalls of the metallic plate (#177b) contact the dielectric material portion ().
However, in analogous art, Nishida teaches:
See embodiment shown in Fig. 32. See also [0163].
wherein the sidewalls of the metallic plate (#916) contact the dielectric material portion (#165/265).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Nishida to the device disclosed by Jung and form the metal pad such that a portion of the metal pad ahs sidewalls that contact the dielectric material portion. Doing so would be a simple substitution of one known backside metallic contact pad/structure for another to achieve the predictable result of forming an electrical pathway between a via structure, like Akio discloses (pad #488 to external wire #719 in Fig. 32).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0202458 A1 Jung et al.
Regarding Claim 9, Jung discloses: The semiconductor structure of Claim 5,
In an alternative embodiment shown in Fig. 6C, Jung discloses:
wherein the backside contact pad (#177b) comprises a horizontal surface that contacts a horizontal bottom surface of the buffer dielectric layer (#120a).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider utilizing the backside contact structure shown in Fig. 6C instead of the generic backside contact structure shown in Fig. 3. Doing so would be a simple substitution of an equivalent structure for another to achieve the purpose of providing an electrical pathway between via structures and external wiring structures.
Claims 11, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0202458 A1 Jung et al in view of US 2022/0093629 A1 Kim et al.
Regarding Claim 11, Jung discloses:
A semiconductor structure (#1, see generally the generic embodiment shown in Fig. 3 and view of memory cell shown in Fig. 4, reference may be made to other embodiments when specified), comprising:
an alternating stack of insulating layers (#120b) and electrically conductive layers (#150, comprising elements #152, #154, #156) that is located on a front side (bottom side with respect to Fig. 3) of at least one semiconductor material layer (#177a, [0044]);
memory openings (Fig. 4, #130) vertically extending through the alternating stack (#120b, #150); memory opening fill structures (shown in Fig. 4, includes elements that lie within width #W1) located in the memory openings (#130) and comprising a respective vertical semiconductor channel (#136) and a respective vertical stack of memory elements (#134b, [0076]);
a dielectric material portion (#120c) laterally offset from the alternating stack (#120b, #150);
a connection via structure (#166a) vertically extending through the dielectric material portion (#120c);
a backside metal via structure (#190) in contact with (in electrical contact) the connection via structure (#166a); and
a backside contact pad (#179b) in contact with the backside metal via structure (#190), wherein the connection via structure (#166a) has a first variable width that increases with a vertical distance from the backside contact pad (#179b);
Jung does not explicitly disclose:
the backside metal via structure has a second variable width that decreases with the vertical distance from the backside contact pad.
However, in analogous art, Kim teaches:
See generally the embodiment of semiconductor device shown in Fig. 7. See also annotated Fig. 7 below.
the backside metal via structure (via portion of pad structure #LP3) has a second variable width that decreases with the vertical distance from the backside contact pad (width of via structure decreases with respect to distance away from contact pad #LP3, see Fig. 7).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kim to the device disclosed by Jung and substitute the backside via structure of Kim (via portion of #LP3) with a variable cross-sectional area that decreases with the vertical distance from the backside contact pad for the backside via structure disclosed by Jung. Doing so would be a simple substitution of one known via structure for another to achieve a predictable result of forming an electrical pathway for the TSV element (#166a in Jung and #TSV in Kim).
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Kim Fig. 7 – Annotated by Examiner
Regarding Claim 12, Jung in view of Kim discloses: The semiconductor structure of Claim
Jung in view of Kim does not explicitly disclose:
further comprising a dielectric backside opening fill structure in contact with a sidewall of the at least one semiconductor material layer and in contact with a bottom surface of the dielectric material portion, a sidewall of the connection via structure, and a sidewall of the backside metal via structure.
However, in analogous art, Kim further teaches:
See generally the embodiment of semiconductor device shown in Fig. 7. See also annotated Fig. 7 above.
further comprising a dielectric backside opening fill structure (see annotated Fig. 7 above) in contact with a sidewall of the at least one semiconductor material layer (#SP, #SC, [00]) and in contact with a bottom surface of the dielectric material portion (#120, [00]), a sidewall of the connection via structure (#TP1-3), and a sidewall of the backside metal via structure (see annotated Fig. 7 above).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kim to the device disclosed by Jung in view of Kim and include a dielectric fill structure to the backside of the device. Doing so would further electrically isolate the individual via structures increasing the overall efficiency of the device.
Regarding Claim 14, Jung in view of Kim discloses: The semiconductor structure of Claim 11,
Jung further discloses:
wherein a horizontal surface of the connection via structure (#166a) contacts a horizontal surface of the backside metal via structure (#190).
Note, under the broadest reasonable interpretation, the term “contacts” can be interpreted as surface-to-surface contact, electrical contact, contact with an intervening layer... etc. For the purposes of examination, “contacts” will be interpreted as electrically contacts, as the bottom surface of the connection via structure electrically connected to the top surface of the connection via structure #190, thus reading on the claimed limitation.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0093629 A1 Kim et al in view of US 2021/0202458 A1 Jung et al.
Regarding Claim 17, Kim discloses: The method of Claim 16,
Kim discloses:
the at least one semiconductor material layer (#SC, #SP) is formed on a top surface of the metallic source structure (#leftmose #PLP that lies in #CAR and #CNR1).
Kim does not explicitly disclose:
further comprising forming a metallic source structure concurrently with formation of the metallic plate, wherein:
the metallic source structure and the metallic plate have a same material composition and a same thickness; and
the at least one semiconductor material layer is formed on a top surface of the metallic source structure.
However, in analogous art, Jung teaches:
further comprising forming a metallic source structure (#175a) concurrently (see [0043]-[0045]) with formation of the metallic plate (#175b), wherein:
the metallic source structure (#175a) and the metallic plate (#175b) have a same material composition and a same thickness (see [0043]-[0045]); and
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the method taught by Jung to the method disclosed by Kim and form the backside source structure concurrently with the backside metallic plate. Kim is silent on the formation of the two elements that appear in Fig. 27A, and appear to have the claimed properties, therefore, a person skilled in the art would seek the teachings of Jung to form the device of Kim.
Regarding Claim 18, Kim in view of Jung discloses: The method of Claim 16,
wherein the at least one semiconductor material layer (#SC, #SP) is formed on a top surface of the buffer dielectric layer (#101, Fig. 27A).
Regarding Claim 19, Kim in view of Jung discloses: The method of Claim 16,
Kim further discloses:
further comprising forming a via opening (#VH1-4) through the buffer dielectric layer (#101), wherein the metallic plate (#LP1-3) comprises a metallic via portion (middle tapered portion) that is formed in the via opening (#VH1-4), and the backside contact pad (#PLP) is formed on a bottom surface of the metallic via portion (middle tapered portion).
Regarding Claim 20, Kim in view of Jung discloses: The method of Claim 16,
Kim further discloses:
further comprising forming a via opening (#VH1-4) through the buffer layer (#101), wherein the backside contact pad (#PLP) comprises a backside metallic via portion (middle tapered portion) that is formed in the via opening (#VH1-4) directly on a backside surface of the metallic plate (#LP1-3).
Allowable Subject Matter
Claims 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 13: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “wherein a top surface of the backside contact pad contacts the dielectric backside opening fill structure.”
Regarding Claim 13: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “further comprising a source-side metal layer underlying the at least one semiconductor material layer, having a same thickness and a same material composition as the backside contact pad, and electrically connected to the at least one semiconductor layer through at least one backside source contact via structure.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812