Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/10/2023 and 12/20/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Arguments
Applicant’s arguments, see remarks (pages 1-2), filed on 10/20/2025, with respect to the restriction requirement of claims 1-9 have been fully considered and are persuasive. The restriction requirement of claims 1-17 and 21-23 has been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwong et al. (US Pat. 7,327,199).
Regarding claim 1, Kwong et al. teaches a system for testing a circuit, the system comprising: a phase-locked loop (200); a test logic circuit (320), the test logic circuit (320) being coupled to the phase-locked loop (200) (as shown in fig. 2), the test logic circuit (320) being configured to count a number of clock cycles (using counter B) of the phase-locked loop using a reference clock (FREF) as a reference, the reference clock being coupled to the test logic circuit (320) (as shown in fig. 2); and a test controller (330), the test controller (330) being coupled to the phase-locked loop (200) and to the test logic circuit (320) (as shown in fig. 2), the test controller (330) being configured to measure a clock frequency (counted by counter A) of the phase-locked loop (measure the frequency of high voltage pulses supplied to the reference clock pin, as disclosed in col. 7, lines 20-31) with the counted number of clock cycles (counted by counter B) received from the test logic circuit (320) (as shown in fig. 2).
Regarding claim 2, Kwong et al. teaches the limitations of claim 1, in addition, Kwong et al. teaches wherein the test logic circuit (320) is further configured to count a number of cycles of the reference clock between an activation time of the phase-locked loop (200) and a locked state time of the phase-locked loop (200) (as disclosed in col. 7, line 9 through col. 9, line 42).
Regarding claim 3, Kwong et al. teaches the limitations of claim 2, in addition, Kwong et al. teaches wherein the test logic circuit (320) is further configured to provide a lock status signal to the test controller (330) based on the counted number of cycles of the reference clock (FREF) between the activation time of the phase-locked loop (200) and the locked state time of the phase-locked loop (200) (as disclosed in col. 7, line 9 through col. 9, line 42).
Regarding claim 4, Kwong et al. teaches the limitations of claim 2, in addition, Kwong et al. teaches wherein the test logic circuit (320) comprises a reference cycles counter (340), the reference cycles counter being configured to set a window over which the number of clock cycles of the phase-locked loop are counted (as disclosed in col. 8, lines 45-65).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kwong et al. (US Pat. 7,327,199) in view of Kao (US Pat. 4,245,211).
Regarding claim 5, Kwong et al. teaches the limitations of claim 4.
Kwong et al. fails to specifically teach wherein the test logic circuit further comprises a delay reference counter, the delay reference counter being configured to enable the reference cycles counter after a delay time. However, Kao teaches wherein the test logic circuit further comprises a delay reference counter, the delay reference counter being configured to enable the reference cycles counter after a delay time (as disclosed in col. 4, lines 53-61).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the test logic circuit further comprise a delay reference counter, the delay reference counter being configured to enable the reference cycles counter after a delay time as taught by Kao with the invention of Kwong et al. in order to allow the PLL to lock up on desired instances and provide a look-ahead capability (Kao col. 4, lines 53-61).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kwong et al. (US Pat. 7,327,199) in view of Li et al. (US Pat. 11,533,045).
Regarding claim 6, Kwong et al. teaches the limitations of claim 1.
Kwong et al. fails to specifically teach wherein the test logic circuit comprises a clock gating cell, the clock gating cell being configured to gate a clock signal from the phase-locked loop. However, Li et al. teaches wherein the test logic circuit comprises a clock gating cell (140), the clock gating cell being configured to gate a clock signal from the phase-locked loop (115) (as disclosed in col. 2, lines 49-64).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the test logic circuit comprise a clock gating cell, the clock gating cell being configured to gate a clock signal from the phase-locked loop as taught by Li et al. with the invention of Kwong et al. in order to gate the clock signal to save power (Li et al. col. 4, lines 49-64).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kwong et al. (US Pat. 7,327,199) in view of Ramsdale (US PGPUB 2006/0182149).
Regarding claim 7, Kwong et al. teaches the limitations of claim 1.
Kwong et al. fails to specifically teach wherein the test controller is controlled using an advanced peripheral bus interface, the advanced peripheral bus interface being coupled to the test controller through a bridge. However, Ramsdale teaches wherein the test controller is controlled using an advanced peripheral bus interface (196b), the advanced peripheral bus interface being coupled to the test controller through a bridge (as shown in fig. 1C and disclosed in para. 0046).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the test controller controlled using an advanced peripheral bus interface, the advanced peripheral bus interface being coupled to the test controller through a bridge as taught by Ramsdale with the invention of Kwong et al. in order to reduce complexity.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kwong et al. (US Pat. 7,327,199) in view of YAMAGIWA (US PGPUB 2022/0246228).
Regarding claim 8, Kwong et al. teaches the limitations of claim 1.
Kwong et al. fails to specifically teach wherein the test controller is further configured to use an IEEE 1149.1, IEEE 1149.x, IEEE 1500, or IEEE 1687 interface. However, YAMAGIWA teaches wherein the test controller is further configured to use an IEEE 1149.1, IEEE 1149.x, IEEE 1500, or IEEE 1687 interface (as shown in fig. 10 and disclosed in para. 0040-0044).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have the test controller further configured to use an IEEE 1149.1, IEEE 1149.x, IEEE 1500, or IEEE 1687 interface as taught by YAMAGIWA with the invention of Kwong et al. in order to have a mechanism to test the internal circuitry of the system and the interconnections without requiring direct physical access.
Regarding claim 9, Kwong et al. teaches the limitations of claim 1.
Kwong et al. fails to specifically teach wherein the test controller is further configured to run a built-in self test. However, YAMAGIWA teaches wherein the test controller is further configured to run a built-in self test (as shown in fig. 10 and disclosed in para. 0040-0044).
It would have been obvious, before the effective filing date of the claimed invention, to one of ordinary skill in the art to combine and have wherein the test controller is configured to run a built-in self test as taught by YAMAGIWA with the invention of Kwong et al. in order to have the ability to inspect the operation of the system without external interference.
Allowable Subject Matter
Claims 10-17 and 21-23 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, the prior art fails to specifically teach a system for testing a circuit, the system comprising: a test logic circuit, the test logic circuit being coupled to the phase-locked loop, the test logic circuit comprising: a lock cycles counter, the lock cycles counter being configured to count a number of cycles of a reference clock between an activation time of the phase-locked loop and a locked state time of the phase-locked loop, the reference clock being coupled to the test logic circuit; and a fast cycles counter, the fast cycles counter being configured to count a number of fast clock cycles of the phase-locked loop using the reference clock as a reference; and a test controller, the test controller being coupled to the phase-locked loop and to the test logic circuit, the test controller being configured to receive a lock cycles count signal from the lock cycles counter and a fast cycles count signal from the fast cycles counter, in combination with all the limitations of the claim.
Claims 11-13 and 15, depending from claim 10; claim 14 depending from claim 13; claim 16 depending from claim 15; and claim 17 depending from claim 16 are allowed for having the same allowable subject matter as disclosed above for claim 10.
Regarding claim 21, the prior art fails to specifically teach system for testing a circuit, the system comprising: a test logic circuit, the test logic circuit being coupled to the phase-locked loop, the test logic circuit comprising: a lock cycles counter, the lock cycles counter being configured to count a number of cycles of a reference clock between an activation time of the phase-locked loop and a locked state time of the phase-locked loop, the reference clock being coupled to the test logic circuit; and a fast cycles counter, the fast cycles counter being configured to count a number of fast clock cycles of the phase-locked loop using the reference clock as a reference; and a test controller, the test controller being coupled to the phase-locked loop and to the test logic circuit, the test controller being configured to receive the counted number of clock cycles and a lock cycles count signal from the lock cycles counter, to receive a fast cycles count signal from the fast cycles counter, and to measure a clock frequency of the phase-locked loop with the counted number of clock cycles received from the test logic circuit, in combination with all the limitations of the claim.
Claims 22 depending from claim 21 and claim 23 depending from claim 22 are allowed for having the same allowable subject matter as disclosed above for claim 21.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pendurkar (US PGPUB 2009/0201057) teaches a method and apparatus to generate system clock synchronization pulses using a PLL lock detect signal.
Srinivasan et al. (US Pat. 11,714,131) teaches a circuit and method for scan testing.
Tzeng et al. (US Pat. 9,157,957) teaches a PLL status detection circuit and method thereof.
Sul (US Pat. 7,793,179) teaches test lock control structures to generate configurable test clocks for scan-based testing od electronic circuits using programmable test clock controllers.
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/ROBERTO VELEZ/Primary Examiner, Art Unit 2858