Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Elections/Restrictions
Applicant’s election without traverse of Species A directed to claims 1-14 in the reply filed on 01/06/2026 is acknowledged. Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/06/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/10/2023 has been considered by the examiner and made of record in the application file.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; or
(a) (2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1, 2, and 7 are rejected under 35 U.S.C 102(a)(1) as being anticipated by Kim et al., US Patent Pub. No. 20230125546A1, hereinafter “Kim.”
Claim 1, 2, and 7 are rejected under 35 U.S.C 102(a)(1) as being anticipated by Kim et al., US Patent Pub. No. 20230125546A1, hereinafter “Kim.”
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Regarding claim 1, Kim teaches semiconductor package (semiconductor package in para [0036] referencing photonic semiconductor package in FIGS. 6 a and 6 b), comprising:
a semiconductor element (interposer #152), having a first side and a second side opposing to the first side;
at least one electronic die (semiconductor die #104 b and conductive layers #196 is an electronic die), disposed over the first side (right side of the package);
at least one optical die, disposed over the first side (#104 a contains photonic circuitry as it is placed in photonic region #176 thus is it an optical die) and next to the at least one electronic die (the optical die #104 a is beneath and next to electronic die #104 b);
an encapsulant (encapsulant #200 in FIG. 6), disposed on the first side and covering the at least one electronic die (encapsulant #200 in FIG. 6 covers the electronic die), wherein a sidewall of the at least one optical die is distant from the encapsulant (encapsulant #200 is placed farther away from the sidewall), and
a sidewall of the encapsulant is aligned with a sidewall of the semiconductor element (encapsulant #200 has a sidewall that is shared with interposer #152); and
a substrate (substrate #190 disposed on the second side), disposed over the second side,
wherein the at least one electronic die is electrically coupled to the substrate (electronic die which is semiconductor die #104 b is coupled to the substrate through conductive layers #156 and pillars #170) and the at least one optical die (semiconductor die #104 a which is the optical die with a photonic region is coupled to interposer #152 which is the semiconductor element through conductive pillars #170 and conductive layers #156) through the semiconductor element (the optical die which is semiconductor die #104 a coupled to interposer #152 which is the semiconductor element through conductive pillars #170 and conductive layers #156).
Regarding claim 2, Kim teaches the semiconductor package of claim 1, wherein the encapsulant (encapsulant #200 in FIG. 6) further comprises an extended portion (the encapsulant #200 which is shaded with diagonal lines in FIG. 6 a above is) disposed between the semiconductor element (interposer #152) and the at least one optical die (semiconductor die #104 a which is the optical die with a photonic region is coupled to interposer #152 which is the semiconductor element through conductive pillars #170 and conductive layers #156),
and the at least one optical die (semiconductor die #104 a) is further free from the extended portion of the encapsulant (the semiconductor die #104 a is not and free from the extended portion of encapsulant #200 in the region #176 is where the encapsulant #200 extends),
wherein a thickness of the extended portion of the encapsulant (the encapsulant #200 with the thickness towards the right end is less and thinner) is less than a thickness of the encapsulant (the right end of the encapsulant #200 around #176 is) covering the at least one electronic die (the encapsulant #200 is covering the semiconductor die #104 a).
Regarding claim 7, Kim teaches the semiconductor package of claim 1,
wherein the encapsulant (encapsulant #200 in FIG. 6) comprises at least one first portion (the encapsulant #200 which is shaded with diagonal lines in FIG. 6 a above is a first portion) disposed between the semiconductor element (interposer #152) and the at least one optical die (semiconductor die #104 a which is the optical die with a photonic region is coupled to interposer #152 which is the semiconductor element through conductive pillars #170 and conductive layers #156) and a second portion (the encapsulant #200 with the thickness towards the right end is less and thinner is the extended portion) surrounding the at least one electronic die (the encapsulant #200 is covering the semiconductor die #104 a),
and the first portion (the first portion of encapsulant #200 on the left side) is connected to the second portion (the second portion of encapsulant #200 on the right side which is thinner is connected to the thicker portion),
wherein in a vertical projection on a plane view (if the cross section of FIG. 6 a is looked at in plane view), the at least one first portion (the first portion of encapsulant #200 on the left side) is disposed near and extends along at least one edge of the semiconductor element (the first portion of encapsulant #200 on the left side is disposed near and extends along one edge of the semiconductor element and is aligned with interposer #152).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § which forms the basis for all obviousness rejections set forth in this office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 6 are rejected under 35 U.S.C § 103 as being unpatentable over Kim in view of Chiu et al. US Patent Pub. No. 20240243068A1, hereinafter “Chiu.”
Regarding claim 4, Kim teaches the semiconductor package of claim 1, wherein the at least one electronic die (semiconductor die #104 b) comprises at least one first die (first die #170) and at least one second die (second die #170).
Kim does not teach wherein the at least one first die and the at least one second die (high bandwidth memory dies #134) are encapsulated in the encapsulant, and the at least one first die and the at least one second die are electrically coupled to the semiconductor element.
However, Chiu teaches wherein the at least one first die (computation die #132 in FIG. 1 as cited in para [0018]) and the at least one second die (high bandwidth memory dies #134 in FIG. 1 as cited in para [0020]) are encapsulated in the encapsulant (they are encapsulated amongst encapsulant layer #160 in para [0022] and shown in FIG. 1), and the at least one first die (computation die #132 in FIG. 1 and para [0018]) and the at least one second die (high bandwidth memory dies #134 in FIG. 1) are electrically coupled (electrically coupling of dies #132 and #134 in FIG. 1 to microbumps #1321 and #1341) to the semiconductor element (microbumps #1321 and #1341 which is connected to the redistribution layer (RDL) #120 and silicon interposer #110 which is the semiconductor element).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to consider providing a semiconductor package with a first and second electronic die as taught in Kim and include the dies to be encapsulated in the encapsulant as shown in Chiu because Chiu explicitly described having computational nodes #130 that includes dies #132 and #134 having an encapsulating layer #160 surrounding the computation nodes #130 as described in step #270 in FIG. 4 and supported by paragraph [0045] of Chiu. A person of ordinary skill in the art would know to apply Chiu’s structure which includes encapsulating multiple semiconductor dies within an encapsulating layer and applying that to the semiconductor package of Kim to provide encapsulation protection for both the first and second dies while maintaining the dies within the same semiconductor package in order to protect and integrate multiple semiconductor dies within a semiconductor package. Accordingly, the combination of Kim and Chiu teaches or suggests the claimed arrangement in which at least one first die and the at least one second die are encapsulated in the encapsulant. Thus, Chiu cures the deficiencies of Kim.
Regarding claim 6, Kim in view of Chiu teaches semiconductor package of claim 4, wherein the at least one first die comprises one or more logic dies (Chiu, computation dies #132 in para [0018] are logic dies), and the at least one second die comprises one or more memory dies (Chiu, high bandwidth memory (HBM) dies #134 in para [0020] are memory dies), and
wherein the semiconductor element comprises an interposer (silicon interposer #110 in FIG. 1 and in para [0017] is a semiconductor element within semiconductor package #100).
Claims 8, 9, 10, and 14 are rejected under 35 U.S.C § 103 as being unpatentable over Kim in view of Lin et al. US Patent Pub. No. 20220149030A1, hereinafter “Lin.”
Regarding claim 8, Kim teaches semiconductor package (semiconductor package in para [0036] referencing photonic semiconductor package in FIGS. 6 a and 6 b), comprising:
a first semiconductor die (semiconductor die #104 b and conductive layers #196 is an electronic die) and a second semiconductor die (#104 a contains photonic circuitry as it is placed in photonic region #176 thus is it an optical die), disposed over and electrically coupled (electronic die which is semiconductor die #104 b is coupled to the substrate through conductive layers #156 and pillars #170) to a semiconductor element (coupled to interposer #152 which is the semiconductor element through conductive pillars #170 and conductive layers #156);
a substrate (substrate #190 disposed on the second side), disposed over and electrically coupled to the semiconductor element (electronic die which is semiconductor die #104 b is coupled to the substrate through conductive layers #156 and pillars #170), the semiconductor element being between the first semiconductor die and the substrate (substrate #190 disposed on the second side).
However, Kim does not teach a first insulating encapsulation,
disposed over the semiconductor element and covering the second semiconductor die;
a second insulating encapsulation,
disposed between the semiconductor element and the first semiconductor die,
the first insulating encapsulation connecting to the second insulating encapsulation, wherein a first thickness of the first insulating encapsulation is greater than a second thickness of the second insulating encapsulation.
However, Lin does teach a first insulating encapsulation (insulating encapsulation #160 in FIG. 21),
disposed over the semiconductor element (second insulating encapsulation #160a is disposed over interposer INT in FIG. 21) and covering the second semiconductor die (the second semiconductor die #120 b is covered with second insulating encapsulation #160 in FIG. 21 with semiconductor dies #120 b covering first insulating encapsulation #130a’);
a second insulating encapsulation (first insulating encapsulation #130a’ in FIG. 21),
disposed between the semiconductor element (first insulating encapsulation #130a’ is disposed between interposer INT in FIG. 21) and the first semiconductor die (#120 a is the first semiconductor die mounted on the interposer INT as described initially in para [0014] and FIG. 21),
the first insulating encapsulation (second insulating encapsulation #160) connecting to the second insulating encapsulation (first insulating encapsulation #130a’), wherein a first thickness of the first insulating encapsulation (the thickness of the second insulating encapsulation #160 is thicker) is greater than a second thickness of the second insulating encapsulation (the thickness of the second insulating encapsulation #160 is thicker than the first insulating encapsulation #130a’).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to consider providing a semiconductor package with a first and second electronic die as taught in Kim and both first and second insulating encapsulations with differing thicknesses as taught in Lin because Lin explicitly teaches the use of multiple insulating encapsulation structures in an interposer based semiconductor package including a first insulating encapsulation and second insulating encapsulation position relative to the semiconductor element and semiconductor die. A person of ordinary skill in the art would know to apply Lin’s structure and encapsulation arrangement to provide separate encapsulation of respective package regions to protect and support the dies and interposer while maintaining Kim’s existing electrical connections and package architecture. Combining Lin’s package structure with that of Kim would provide encapsulation protection for multiple dies and the interposer within the same semiconductor package. Accordingly, the combination of Kim and Lin teaches or suggests the claimed arrangement in which there are a first and second insulating encapsulations as shown in FIG. 21. Thus, Lin cures the deficiencies of Kim.
Regarding claim 9, Kim in view of Lin teaches a semiconductor package of claim 8, further comprising at least one of:
a first underfill (underfill UF1 in para [0016]), disposed between the first semiconductor die (semiconductor die #120 a in FIG. 21) and the second insulating encapsulation (first insulating encapsulation #130’a in FIG. 21) and wrapping a plurality of first bonding structures (first conductive bumps #122 a ) disposed between and physically connecting the first semiconductor die (connects wafer “W” initially introduced in FIG. 2 of the process and first semiconductor die #120 a) and the semiconductor element (interposer INT in FIG. 21 is connected to both the first conductive bumps #122 a and first semiconductor die #120 a);
a second underfill (second underfill UF2), disposed between the second semiconductor die (second semiconductor die #120 b) and the semiconductor element (interposer INT in FIG. 21) and wrapping a plurality of second bonding structures (second conductive bumps #122 b ) disposed between and physically connecting the second semiconductor die (connects wafer “W” initially introduced in FIG. 2 of the process and second semiconductor die #120 b) and the semiconductor element (interposer INT in FIG. 21 is connected to both the second conductive bumps #122 b and second semiconductor die #120 b); or
a third underfill (UF3 is the third underfill shown in FIG. 10 in para [0037]), disposed between the semiconductor element (INT interposer in FIG. 10) and the substrate (circuit board #200) and wrapping third bonding structures (circuit board #200 surrounds and wraps conductive terminals #152) disposed between and physically connecting the semiconductor element and the substrate (UF3 is disposed between the wiring substrate #150 and circuit board #200 which includes a semiconductor substrate and fills a gap between the CoWoS package structure P1 in para [0037]-[0038]).
Regarding claim 10, Kim in view of Lin teaches the semiconductor package of claim 8, further comprises:
a plurality of first conductive terminals (Lin, conductive terminals #152), disposed between and electrically coupling the semiconductor element (Lin, interposer INT) and the substrate (Lin, wiring substrate #150);
an underfill (Lin, UF3), disposed between the semiconductor element (Lin, the thick rectangular block in the center of circuit board #200) and the substrate (Lin, circuit board #200 which is also a substrate in FIG. 10), the underfill (Lin, UF3) wrapping the plurality of first conductive terminals (Lin, UF3 wraps around conductive terminals #152 which is the first conductive terminals in FIG. 10); and
a plurality of second conductive terminals (Lin, conductive pins #310), disposed over and electrically coupling the substrate (Lin, in FIG. 11, conductive pins #310 is disposed over circuit board #200), wherein the substrate (Lin, circuit board #200) is between the plurality of first conductive terminals (Lin, conductive terminals #152) and the plurality of second conductive terminals (Lin, conductive pins #310),
wherein the semiconductor element comprises an interposer (Lin, INT interposer in the middle of #200).
Regarding claim 14, Kim in view of Lin teaches the semiconductor package of claim 8, wherein in
a stacking direction of the first semiconductor die (Lin, semiconductor die #120 a in FIG. 10) and the semiconductor element (Lin, INT interposer in FIG. 10),
the second insulating encapsulation (second insulating encapsulation #130 a’) has a second outermost surface (the outermost edge of second insulating encapsulation #130 a’ that is in contact with first insulating encapsulation #160) away from the semiconductor element (INT interposer),
and the second outermost surface (the outermost surface of the second insulating encapsulation #130 a’) comprises two or more portions (bottom portion edge of #130 a’ is next to UF2, second underfill) respectively disposed at different heights (insulating encapsulation #130 a’ and insulating encapsulation #160 are different heights with the top portion of insulating encapsulation #130 a’ is placed higher than the portion of insulating encapsulation #160).
Allowable Subject Matter
Claims 3, 5, and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, Kim teaches the semiconductor package of claim 1, wherein a portion of the encapsulant (encapsulant #200 in FIG. 6 a and 6 b) further between the semiconductor element (interposer #152) and the at least one optical die (#104 a contains photonic circuitry as it is placed in photonic region #176 thus is it an optical die) has an first outermost surface (photonic region #176 is the outermost surface and extended portion of encapsulant #200) with a first surface roughness (photonic region #176 has a separate #176),
and a portion of the encapsulant (encapsulant #200) surrounding the at least one electronic die (semiconductor die #104 b which surrounds the encapsulant and controlled through #156) has an second outermost surface (encapsulant #200 is connected to the outermost surface #204 which is the mold underfill) with a second surface roughness (a separate surface roughness in the outermost surface #204 or the mold underfill),
wherein the first outermost surface (photonic region #176) is free from the semiconductor element (the photonic region #176 is away from and not in contact with interposer #152), and
the second outermost surface (second outermost surface which is the mold underfill #204) is level with a surface of a substrate of the at least one electronic die (semiconductor die #104 b) has an second outermost surface with a second surface roughness (second outermost surface which is the mold underfill #204 has a separate),
Kim does not teach the first surface roughness is greater than the second surface roughness. The prior art of record of Kim does not explicitly teach the first surface roughness is greater than the second surface roughness. Specifically, while the closest prior art of record, Kim may disclose individual concepts such as a first and second surfaces and encapsulants within a semiconductor packaging component, the device specifically does not teach the first surface and second surface having differing surface roughnesses and the specific insight into the roughnesses such as the polishing and planarization processes. Although the prior art discloses semiconductor packaging devices including semiconductor elements, electronic dies, optical dies, and encapsulation structures, it does not teach or suggest intentionally providing different surface roughnesses for the respective encapsulant portions as claimed. Nowhere in Kim are the surface roughness of the respective outermost encapsulant surfaces presented in the disclosure of Kim and the outermost encapsulant surfaces. The prior art of Kim does not teach outermost surfaces having varying degrees of surface roughnesses and their differential relationship to one another. Accordingly, the claimed surface roughness relationship is considered to distinguish the claimed invention over the prior art of record.
Regarding claim 5, Kim in view of Chiu teaches the semiconductor package of claim 4, wherein a portion of the encapsulant (Kim, encapsulant #200 in FIG. 5) further between the semiconductor element (Kim, interposer #152) and the at least one optical die (Kim, semiconductor die #104 a) has an first outermost surface with a first surface roughness, and a portion of the encapsulant further between the at least one first die and the at least one second die has an second outermost surface with a second surface roughness, wherein the first outermost surface and the second outermost surface are free from the semiconductor element, and the first surface roughness is greater than the second surface roughness.
However, Kim and Chiu do not teach one optical die (Kim, semiconductor die #104 a) having an first outermost surface with a first surface roughness, and a portion of the encapsulant further between the at least one first die and the at least one second die has an second outermost surface with a second surface roughness, wherein the first outermost surface and the second outermost surface are free from the semiconductor element, and the first surface roughness is greater than the second surface roughness.
Kim and Chiu does not teach a one optical die (Kim, semiconductor die #104 a) having an first outermost surface with a first surface roughness, and a portion of the encapsulant further between the at least one first die and the at least one second die has an second outermost surface with a second surface roughness, wherein the first outermost surface and the second outermost surface are free from the semiconductor element. The prior art of record of Kim or Lin does not explicitly teach having an first outermost surface with a first surface roughness, and a portion of the encapsulant further between the at least one first die and the at least one second die has an second outermost surface with a second surface roughness, wherein the first outermost surface and the second outermost surface are free from the semiconductor element. Specifically, while the closest prior art of record, Kim and Chiu combined may disclose individual concepts such as a first and second surfaces and encapsulants within a semiconductor packaging component, the first and second dies such as the optical and electronic die being coupled to the same element while being encapsulated between and in the encapsulant. Kim and Chiu do not disclose a first outermost surface and second outermost surface within an encapsulant having the claimed differential surface roughness relationship between these specific respective potions of the semiconductor package, and it Therefore, these limitations distinguish the claimed invention over the prior art of record.
Regarding claim 11, Kim in view of Lin teaches the semiconductor package of claim 8, further comprising:
a third semiconductor die (Lin, #120 b there are two semiconductor die labeled #120 b in FIG. 21), disposed over and electrically coupled to the semiconductor element (Lin, INT interposer in FIG. 21) and next to the second semiconductor die (the first #120 b semiconductor die and the second #120 b die are placed together in a top down view in FIGS. 13), wherein the third semiconductor die is covered by the first insulating encapsulation (Lin, insulating encapsulation layer 130 a’ surrounds #120 and cover the edges of #120 b for both #120 b dies in FIG. 21).
However, Kim does not teach a fourth underfill, disposed between the third semiconductor die and the semiconductor element and wrapping a plurality of fourth bonding structures disposed between and physically connecting the third semiconductor die and the semiconductor element.
Kim and Lin does not teach a fourth underfill, disposed between the third semiconductor die and the semiconductor element and wrapping a plurality of fourth bonding structures disposed between and physically connecting the third semiconductor die and the semiconductor element. The prior art of record of Kim or Lin does not explicitly teach a fourth underfill, disposed between the third semiconductor die and the semiconductor element and wrapping a plurality of fourth bonding structures disposed between and physically connecting the third semiconductor die and the semiconductor element. Although, Lin teaches the third semiconductor die and first insulating encapsulation surrounding the third semiconductor die and a third underfill, Lin does not disclose a separate fourth underfill disposed between the third semiconductor die and the semiconductor element and the surrounding plurality of bonding structures connecting the third semiconductor die to the semiconductor element. Accordingly, claim 11 contains allowable subject matter as both Kim and Lin in combination fail to teach or suggest the fourth underfill and depict a fourth underfill associated with fourth bonding structures. Thus, the combination of Kim and Lin does not teach or suggest this limitation.
Dependent claim 12 depend directly or indirectly from dependent claim 11 and, thus, further define and/or limit the subject matter recited therein. Therefore, dependent claim 12 also contains allowable subject matter.
Regarding claim 13, Kim in view of Lin teaches the semiconductor package of claim 8, wherein in a stacking direction of the first semiconductor die (Kim, semiconductor die #104 b) and the semiconductor element (Kim, interposer #152),
the first insulating encapsulation (Lin, insulating encapsulation #160a) has a first outermost surface away from the semiconductor element,
and the second insulating encapsulation (Lin, insulating encapsulation #130 a’) has a second outermost surface away from the semiconductor element,
wherein a first surface roughness of the first outermost surface is less than a second surface roughness of the second outermost surface.
However, Kim does not teach the first insulating encapsulation has a first outermost surface away from the semiconductor element,
and the second insulating encapsulation has a second outermost surface away from the semiconductor element,
wherein a first surface roughness of the first outermost surface is less than a second surface roughness of the second outermost surface.
Kim and Lin does not teach the first insulating encapsulation has a first outermost surface away from the semiconductor element, and the second insulating encapsulation has a second outermost surface away from the semiconductor element, wherein a first surface roughness of the first outermost surface is less than a second surface roughness of the second outermost surface. The prior art of record of Kim or Lin does not explicitly teach the first insulating encapsulation has a first outermost surface away from the semiconductor element, and the second insulating encapsulation has a second outermost surface away from the semiconductor element, wherein a first surface roughness of the first outermost surface is less than a second surface roughness of the second outermost surface. Specifically, while the closest prior art of record, Kim and Lin teaches a first and second surfaces existing within outermost surface of the first and second insulating encapsulations and the two varying encapsulation structures within a semiconductor packaging component, Kim and Lin do not teach or suggest that the first surface roughness of those outermost surface is less than the second surface roughness of the second outermost surface. The differential surface roughnesses between the first and second insulating encapsulations are not disclosed. Therefore, these limitations distinguish the claimed invention over the prior art of record.
Conclusion
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/MEHEK AHMED/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights