DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Masuoka et al. (Masuoka, US 2010/0219483 A1).
Regarding claims 1 and 13, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) device comprising: a vertical channel (channel 722b/721a/723b in FIG. 27a); a memory microdevice connected ( by contact 707a and [0120-0130]) to the vertical channel ( channel 722b/721a/723b in FIG. 27a), the memory microdevice comprising a memory cell ( by memory contact 707a) in direct contact with to a sidewall ( electrode 718a) of the vertical channel ( channel 722b/721a/723b in FIG. 27a); and a logic microdevice (Qp28) connected to the vertical channel, the logic microdevice comprising a logic-gate insulator (insulator 734) in direct contact with to the sidewall of the vertical channel (channel 722b/721a/723b in FIG. 27a).
Regarding claim 2, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d), wherein the memory microdevice further comprises: a memory-gate ( electrode 718a) in direct contact with to a sidewall of the memory cell ( element 707a).
Regarding claim 3, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d), wherein the logic microdevice further comprises: a logic-gate (electrode 718a) in direct contact with to a sidewall of the logic-gate insulator ( insulator 734).
Regarding claim 4, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d), further comprising: a top source/drain ( 716/704b) in direct contact with to a top surface of the vertical channel ( channel 721a).
Regarding claim 5, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising: a bottom source/drain (704b) in direct contact with to a bottom surface of the vertical channel (cannel 721a).
Regarding claim 6, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising: a first frontside contact in direct contact with to a top surface of the memory-gate ([0120-0130], 715, and FIG. 27a-27d).
Regarding claim 7, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) a second frontside contact (706a)in direct contact with to a top surface of the top source/drain (714).
Regarding claim 8, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising: a first backside contact in direct contact with to a bottom surface of the logic-gate (see FIG. 26).
Regarding claim 9, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising a second backside contact in direct contact with to a bottom surface of the bottom source/drain (see FIG. 26-27d).
Regarding claim 10, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising a frontside back end of line (BEOL) network in direct contact with to the first frontside contact and the second frontside contact (see FIG. 26-27d).
Regarding claim 11, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising a backside BEOL network in direct contact with to the first backside contact and the second backside contact (see FIG. 26-27d).
Regarding claim 12, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising, wherein the second frontside contact, the top source/drain, the vertical channel, the bottom source/drain , and the second backside contact are vertically inline (see FIG. 26-27d).
Regarding claim 14, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) , wherein the memory microdevice further comprises: a memory-gate around and against each of one or more sidewalls of the memory cell (see FIG. 26-27d).
Regarding claim 15, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising wherein the logic microdevice further comprises: a logic-gate around and against each of one or more sidewalls of the logic-gate insulator (see FIG. 26-27d).
Regarding claim 16, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising a top source/drain in direct contact with to a top surface of the vertical channel (see FIG. 26-27d).
Regarding claim 17, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising a bottom source/drain in direct contact with to a bottom surface of the vertical channel(see FIG. 26-27d).
Regarding claim 18, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising a first frontside contact in direct contact with to a top surface of the memory-gate; and a second frontside contact in direct contact with to a top surface of the top source/drain (see FIG. 26-27d).
Regarding claim 19, Masuoka shows a semiconductor integrated circuit (IC) (FIG. 27a-d) further comprising a first backside contact in direct contact with to a bottom surface of the logic-gate; and a second backside contact in direct contact with to a bottom surface of the bottom source/drain (see FIG. 26-27d).
Regarding claim 20, Masuoka shows a method of semiconductor integrated circuit (IC) device fabrication comprising: forming a vertical channel (channel 721a); forming a logic-gate insulator (insulator 734) directly against a sidewall of the vertical channel (channel 721a) and forming a logic-gate (gate electrode 718a) directly against a sidewall of the logic-gate insulator (insulator 734); and forming a memory cell directly (by memory contact 707a) against the sidewall of the vertical channel and forming a memory-gate directly against a sidewall of the memory cell (see FIG. 26 and 27a-d).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893