DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
None filed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Calderoni et al. (U.S. Patent Application Publication 2020/0235111).
Referring to Claim 1, Calderoni teaches in Fig. 12A for example, an integrated assembly (10), comprising: a conductive plate (46; par. 82-83); a top electrode (42; par. 79-80) in contact with the conductive plate (46) and shared by a plurality of bottom electrodes (26; par. 65-66 and 80-81) included in the integrated assembly (10); a bottom electrode (26) having a top surface, a bottom surface, and an exterior circumferential surface; a ferroelectric insulator (38; par. 76) that separates the top electrode (42) from the bottom electrode (26), wherein a support structure is not present between a top surface of the ferroelectric insulator (38) and a bottom surface of the conductive plate (46); and a leaker device (48; par. 84) having a top surface, a bottom surface in contact with the top surface of the bottom electrode (26), and an exterior circumferential surface, wherein the leaker device (48) is configured to discharge charge from the bottom electrode (26) to the conductive plate (46).
Referring to Claim 2, Calderoni further teaches wherein the top surface of the ferroelectric insulator (38) is in contact with the bottom surface of the conductive plate (46).
Referring to Claim 3, Calderoni further teaches wherein the ferroelectric insulator (38) includes multiple non-contiguous top surfaces, along a cross-section of the integrated assembly (10), that are in contact with the bottom surface of the conductive plate (46).
Referring to Claim 4, Calderoni further teaches (see Fig. 11) wherein the multiple non-contiguous top surfaces of the ferroelectric insulator (38) are substantially horizontally aligned with a plurality of top surfaces of a corresponding plurality of leaker devices (48) included in the integrated assembly (10).
Referring to Claim 5, Calderoni further teaches (see Fig. 11) wherein the multiple non-contiguous top surfaces of the ferroelectric insulator (38) are substantially horizontally aligned with a plurality of first top electrode portions of the top electrode (42).
Referring to Claim 6, Calderoni further teaches wherein the top surface of the leaker device (48) is in contact with the bottom surface of the conductive plate (46).
Referring to Claim 7, Calderoni further teaches wherein the top electrode includes: a first top electrode (42) portion that is separated from the bottom electrode (26) by the leaker device (48), wherein the leaker device (48) is configured to discharge charge from the bottom electrode (26) to the conductive plate (46) via the first top electrode (42) portion; and a second top electrode (42) portion that is separated from the bottom electrode (26) by the ferroelectric insulator (38).
Referring to Claim 8, Calderoni further teaches a leaker liner (18) surrounding the exterior circumferential surface of the leaker device (48) (par. 54).
Referring to Claim 9, Calderoni further teaches wherein the top electrode (42), the bottom electrode (26), and the ferroelectric insulator (38) form a capacitor (44; par. 81).
Referring to Claim 10, Calderoni further teaches a plurality of capacitors (44) that share the top electrode (42), wherein each capacitor (44), of the plurality of capacitors (44), includes a corresponding leaker device (48), and wherein all of those leaker devices (48) have at least one of substantially identical electrical properties or substantially identical physical dimensions.
Referring to Claim 11, Calderoni teaches in Fig. 12A, 20 and 21 for example, a memory device (52), comprising: a cell plate (46); and a memory cell (50) that includes: a transistor (49; par. 85 and 100); a bottom electrode (26) electrically coupled with the transistor (49); a leaker device (48) on top of the bottom electrode (26), wherein the leaker device (48) is configured to discharge charge from the bottom electrode (26) to the cell plate (46); a leaker liner (18; par. 54) surrounding an exterior vertical surface of the leaker device; a top electrode (42) shared among a plurality of memory cells (50); and an insulator (38) that separates the top electrode (42) from the bottom electrode (26), wherein a top surface of the insulator (38) is in contact with the cell plate (46).
Referring to Claim 12, Calderoni further teaches wherein the insulator (38) includes multiple non-contiguous top surfaces, along a cross-section of the memory device (52), that are in contact with a bottom surface of the cell plate (46).
Referring to Claim 13, Calderoni further teaches wherein the memory device (52) does not include a support structure between the multiple non-contiguous top surfaces of the insulator (38) and the bottom surface of the cell plate (46).
Referring to Claim 14, Calderoni further teaches wherein a top surface of the leaker device (48) is in contact with a bottom surface of the cell plate (46).
Referring to Claim 15, Calderoni further teaches wherein a portion of the top electrode (42) is on top of the leaker device (48), is under the cell plate (46), and is in contact with both the leaker device (48) and the cell plate (46).
Referring to Claim 16, Calderoni further teaches wherein the leaker device (48) is configured to discharge charge from the bottom electrode (26) to the cell plate (46) via the portion of the top electrode (42).
Referring to Claim 17, Calderoni further teaches wherein each memory cell (50), of the plurality of memory cells (10), includes a corresponding leaker device (48), and wherein all of those leaker devices (48) have substantially identical electrical properties and substantially identical physical dimensions.
Referring to Claim 18, Calderoni teaches in Fig. 1-12A for example, a method, comprising: forming a plurality of bottom electrodes (26); forming a plurality of leaker devices (48), wherein each leaker device (48), of the plurality of leaker devices (48), is situated on top of a corresponding bottom electrode (26) of the plurality of bottom electrodes (26); forming a top electrode (42); forming a ferroelectric insulator (38) in contact with the plurality of bottom electrodes (26) and in contact with the plurality of leaker devices (48), wherein the ferroelectric insulator (38) separates the top electrode (42) from the plurality of bottom electrodes (26); and forming a cell plate (46) that is in contact with a plurality of non-contiguous top surfaces of the ferroelectric insulator (38), wherein each leaker device (48), of the plurality of leaker devices (48), is configured to discharge charge from a corresponding bottom electrode (26) to the cell plate (46).
Referring to Claim 19, Calderoni further teaches wherein respective top surfaces of the plurality of leaker devices (48) are in contact with the cell plate (46).
Referring to Claim 20, Calderoni further teaches forming a plurality of top electrode (42) portions of the top electrode (46), wherein each top electrode (42) portion, of the plurality of top electrode (42) portions, is situated on top of a corresponding leaker device (48) of the plurality of leaker devices (48), and wherein each leaker device (48), of the plurality of leaker devices (48), is configured to discharge charge from a corresponding bottom electrode (26) to the cell plate (46) via a corresponding top electrode (42) portion of the plurality of top electrode (42) portions.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chavan et al. (U.S. Patent Application Publication 2024/0049473).
The applied reference has a common assignee and one common inventor with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Referring to Claim 1, Chavan teaches in Fig. 1, 3, 5A and 5B for example, and an integrated assembly, comprising: a conductive plate (150); a top electrode (140) in contact with the conductive plate (150) and shared by a plurality of bottom electrodes (135) included in the integrated assembly; a bottom electrode (135) having a top surface, a bottom surface, and an exterior circumferential surface; a ferroelectric insulator (145) that separates the top electrode (140) from the bottom electrode (135), wherein a support structure is not present between a top surface of the ferroelectric insulator (145) and a bottom surface of the conductive plate (150); and a leaker device (155) having a top surface, a bottom surface in contact with the top surface of the bottom electrode (135), and an exterior circumferential surface, wherein the leaker device (155) is configured to discharge charge from the bottom electrode (135) to the conductive plate (150).
Referring to Claim 2, Chavan further teaches wherein the top surface of the ferroelectric insulator (145) is in contact with the bottom surface of the conductive plate (150).
Referring to Claim 3, Chavan further teaches wherein the ferroelectric insulator (145) includes multiple non-contiguous top surfaces, along a cross-section of the integrated assembly, that are in contact with the bottom surface of the conductive plate (150).
Referring to Claim 4, Chavan further teaches wherein the multiple non-contiguous top surfaces of the ferroelectric insulator (145) are substantially horizontally aligned with a plurality of top surfaces of a corresponding plurality of leaker devices (155) included in the integrated assembly.
Referring to Claim 5, Chavan further teaches wherein the multiple non-contiguous top surfaces of the ferroelectric insulator (145) are substantially horizontally aligned with a plurality of first top electrode portions of the top electrode (140).
Referring to Claim 6, Chavan further teaches wherein the top surface of the leaker device (155) is in contact with the bottom surface of the conductive plate (150).
Referring to Claim 7, Chavan further teaches wherein the top electrode includes: a first top electrode (140) portion that is separated from the bottom electrode (135) by the leaker device (155), wherein the leaker device (155) is configured to discharge charge from the bottom electrode (135) to the conductive plate (150) via the first top electrode (140) portion; and a second top electrode (140) portion that is separated from the bottom electrode (135) by the ferroelectric insulator (145).
Referring to Claim 8, Chavan further teaches 8. The integrated assembly of claim 1, further comprising a leaker liner (520) surrounding the exterior circumferential surface of the leaker device (155).
Referring to Claim 9, Chavan further teaches wherein the top electrode (140), the bottom electrode (135), and the ferroelectric insulator (145) form a capacitor (110).
Referring to Claim 10, Chavan further teaches a plurality of capacitors that share the top electrode (140), wherein each capacitor (110), of the plurality of capacitors, includes a corresponding leaker device (155), and wherein all of those leaker devices (155) have at least one of substantially identical electrical properties or substantially identical physical dimensions.
Referring to Claim 11, Chavan teaches a memory device, comprising: a cell plate (150); and a memory cell (100) that includes: a transistor (105); a bottom electrode (135) electrically coupled with the transistor (105); a leaker device (155) on top of the bottom electrode (135), wherein the leaker device (155) is configured to discharge charge from the bottom electrode (135) to the cell plate (150); a leaker liner (520) surrounding an exterior vertical surface of the leaker device (155); a top electrode (140) shared among a plurality of memory cells; and an insulator (145) that separates the top electrode (140) from the bottom electrode (135), wherein a top surface of the insulator (145) is in contact with the cell plate (150).
Referring to Claim 12, Chavan further teaches wherein the insulator (145) includes multiple non-contiguous top surfaces, along a cross-section of the memory device, that are in contact with a bottom surface of the cell plate (150).
Referring to Claim 13, Chavan further teaches wherein the memory device does not include a support structure between the multiple non-contiguous top surfaces of the insulator (145) and the bottom surface of the cell plate (150).
Referring to Claim 14, Chavan further teaches wherein a top surface of the leaker device (155) is in contact with a bottom surface of the cell plate (150).
Referring to Claim 15, Chavan further teaches wherein a portion of the top electrode (140) is on top of the leaker device (155), is under the cell plate (150), and is in contact with both the leaker device (155) and the cell plate (150).
Referring to Claim 16, Chavan further teaches wherein the leaker device (155) is configured to discharge charge from the bottom electrode (135) to the cell plate (150) via the portion of the top electrode (140).
Referring to Claim 17, Chavan further teaches wherein each memory cell (100), of the plurality of memory cells, includes a corresponding leaker device (155), and wherein all of those leaker devices have substantially identical electrical properties and substantially identical physical dimensions.
Referring to Claim 18, Chavan teaches a method, comprising: forming a plurality of bottom electrodes (135); forming a plurality of leaker devices (155), wherein each leaker device (155), of the plurality of leaker devices (155), is situated on top of a corresponding bottom electrode (135) of the plurality of bottom electrodes (135); forming a top electrode (140); forming a ferroelectric insulator (145) in contact with the plurality of bottom electrodes (135) and in contact with the plurality of leaker devices (155), wherein the ferroelectric insulator (145) separates the top electrode (140) from the plurality of bottom electrodes (135); and forming a cell plate (150) that is in contact with a plurality of non-contiguous top surfaces of the ferroelectric insulator (145), wherein each leaker device (155), of the plurality of leaker devices (155), is configured to discharge charge from a corresponding bottom electrode (135) to the cell plate (150).
Referring to Claim 19, Chavan further teaches wherein respective top surfaces of the plurality of leaker devices (155) are in contact with the cell plate (150).
Referring to Claim 20, Chavan further teaches forming a plurality of top electrode (140) portions of the top electrode (140), wherein each top electrode (140) portion, of the plurality of top electrode (140) portions, is situated on top of a corresponding leaker device (155) of the plurality of leaker devices (155), and wherein each leaker device (155), of the plurality of leaker devices (155), is configured to discharge charge from a corresponding bottom electrode (135) to the cell plate (150) via a corresponding top electrode (140) portion of the plurality of top electrode (140) portions.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chavan et al. (U.S. Patent Application Publication 2019/0189357) teaches in Fig. 16 (par. 65-74) for example, an integrated assembly (10), comprising: a conductive plate (46; par. 51); a top electrode (36; par. 44) in contact with the conductive plate (46) and shared by a plurality of bottom electrodes (26; par. 31) included in the integrated assembly (10); a bottom electrode (26) having a top surface, a bottom surface, and an exterior circumferential surface; a ferroelectric insulator (30; par. 37) that separates the top electrode (36) from the bottom electrode (26), wherein a support structure is not present between a top surface of the ferroelectric insulator (30) and a bottom surface of the conductive plate (46); and a leaker device (40; par.) having a top surface, a bottom surface in contact with the top surface of the bottom electrode (26), and an exterior circumferential surface, wherein the leaker device (40) is configured to discharge charge from the bottom electrode (26) to the conductive plate (46).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896