DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/6/2026 has been entered.
Claims 1-11 are pending. Claims 2, 4 and 7-8 have been withdrawn. Claim 1 has been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. US 2020/0402997 A1 (Ahn) in view of Kim et al. US 2017/0084626 A1 (Kim).
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In re claim 1, Ahn discloses (FIGs. 3-4 & 12-26) a method of manufacturing a semiconductor device, the method comprising:
forming a stack structure 120,310 including alternately stacked insulating layers 310 and sacrificial layers 120 (FIG. 12, ¶ 55,83);
forming a trench 320H penetrating the stack structure (FIG. 13, ¶ 86);
replacing the sacrificial layers 120 with conductive patterns 130X,130Y (each layer 120 is replaced with stacked structure 20+132+134 including conductive patterns 130X,130Y in the resulting structure as shown in FIGs. 4 & 23);
forming buffer patterns 182 on sidewalls of the conductive patterns 130X,130Y;
forming air gaps 144 by removing the insulating layers 310 (FIGs. 15-17 & 24);
forming a slit insulating layer 146,182 sealing the air gaps 144 (FIGs. 24-26, ¶ 103); and
forming a source contact 180 in contact with the slit insulating layer 146,182 (FIG. 26, ¶ 105);
wherein the slit insulating layer 146,182 includes a first interposition part (part next to 120+130) covering a sidewall of one of the conductive patterns 130X,130Y and a second interposition part (part next to 144) covering one of the air gaps 144;
wherein the source contact 180 includes a first contact part (part next to 120+130) covering the first interposition of the slit insulating layer and a second contact part (part next to 144) covering the second interposition part of the slit insulating layer; and
wherein an interface (146/182 interface next to 120+130) between the first contact part of the source contact 180 and the first interposition part of the slit insulating layer is convex toward the first contact part (part of 180 next to 120+130).
Ahn discloses the claimed invention including a method of manufacturing a 3D memory comprising insulation material 146+182, which includes the buffer patterns 182, covering sidewalls of the gate conductors 130 in a source contact trench prior to forming the source contact 180. Ahn does not explicitly disclose wherein forming the slit insulating layer 146+182 includes oxidizing the buffer patterns.
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However, Kim a method of manufacturing a 3D memory comprising an insulating spacer structure SP covering the sidewalls of the gate electrodes EL in a source contact trench T (FIG. 10) prior to forming the source contact CSP (FIG. 11). Kim further teaches forming the insulating spacer SP comprises (FIGs. 14A-14C & 15) forming buffer patterns 143 (FIG. 13B, ¶ 120) on sidewalls of the conductive patterns EL by conformal coating on insulating layer 141, and wherein forming insulating spacer SP includes oxidizing the buffer patterns 143 (FIG. 14A, ¶ 121). Kim further discloses the insulating spacer SP may have a non-flat surface in contact with the source contact CSP (see FIG. 15). Kim teaches the layer 143 forming the buffer patterns is deposited with excellent step coverage to ensure conformal coating (¶ 107).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Ahn’s insulating spacer 146+182 according to a method taught by Kim which comprises providing a conformal layer (e.g. Kim’s layer 143) on Ahn’s insulating film 146 having uneven surface, to obtain buffer patterns on sidewalls of the conductive patterns 130. And further oxidizing the buffer patterns to form an oxidized layer (e.g. Kim’s layer 147 in FIG. 14A), which defines the insulating surface of the insulating spacer as taught by Kim. The modification would be obvious to one having ordinary skill in the art to form insulating spacer with improved step coverage on uneven surface as taught by Kim.
Furthermore, the source contact may be provided on a subsequently planarized surface of the insulating spacer as taught by Kim’s FIG. 14C, resulting in a convex interface defined by the underlying insulating film 146 adjacent to the conductive gate patterns 130.
Alternatively, as taught by Kim in FIG. 15, the insulating spacer may remain uneven, and the source contact contacting the uneven surface of the insulating spacer, resulting in an additional convex interface defined by the surface of the insulating spacer abutting the source contact adjacent to the conductive gate patterns 130.
In re claim 3, Kim discloses wherein forming the buffer patterns includes (FIG. 14A-14C):
forming oxidation patterns HIL on sidewalls of the insulating layers ILD (¶ 84,136-138); and
forming the buffer patterns 143 between the oxidation patterns HIL (FIG. 14A). Buffer patters 143 are considered vertically between adjacent vertical levels of HIL. No specific vertical overlap or alignment is claimed.
In re claim 9, Kim discloses (e.g. FIG. 14A) wherein forming the buffer patterns 143 includes forming the buffer patterns 143 between the insulating layers ILD. Buffer patters 143 are considered vertically between layers of ILD. No specific vertical overlap or alignment is claimed.
In re claim 10, Kim discloses (e.g. FIG. 10) wherein the buffer patterns 143 include poly-silicon (¶ 120).
In re claim 11, in an alternatively interpretation, the buffer patterns correspond to the combined structure of 141 and 143 as taught by Kim (FIGs. 14A-14C), wherein the buffer patterns 141+143 includes nitride 141 (¶ 102).
Allowable Subject Matter
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior art does not disclose, alone or in combination along with, the limitations of the dependent claim reciting forming the oxidation patterns includes:
forming first recesses by removing a portion of each of the insulating layers through the trench;
forming seed patterns in the first recesses;
forming preliminary oxidation patterns on sidewalls of the seed patterns; and
oxidizing the seed patterns and the preliminary oxidation patterns.
Neither Ahn nor Kim teaches the steps of forming the oxidation patterns as recited in claim 5.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3, and 9-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896