DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11 Oct 2023, 2 Apr 2024, and 17 May 2024 have been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: paragraph 105 states (starting in the 3rd line): “The first upper separation pattern SIP is interposed between … As shown in FIG. 6B, the first upper separation pattern SIP may be disposed between …”. Based on the second sentence of this paragraph, both of these instances of SIP should be changed to SIP1.
Appropriate correction is required.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: paragraph 105 states (starting in the 6th line): “As shown in FIG. 6B, the first upper separation pattern SIP [examiner: SIP1] may be disposed between the cell vertical patterns VS and may have a zigzag shape in a plan view.” However, FIG. 6B does not include a label for VS. Either FIG. 6B should be amended to include a label for VS, or the previously quoted sentence should be amended to specifically refer to FIG. 2, which illustrates the following features from paragraph 105:
“the first upper separation pattern SIP [SIP1] may be disposed between the cell vertical patterns VS and may have a zigzag shape in a plan view. The second upper separation pattern SIP2 may be interposed between the third and fourth upper conductive lines SSL3 and SSL4. The second upper separation pattern SIP2 may have a straight line shape when viewed in a plan view. The second upper separation pattern SIP2 may pass through upper portions of the dummy vertical patterns DVS.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2 is objected to because of the following informality: “wherein” should be inserted at the beginning of the 2nd page of the claims (applicant’s page 53) just before “the second front end and the second back end are connected to …”
Claim 7 is objected to because of the following informality: the 4th line refers to “the end insulation pattern”, which was introduced in the 2nd line as “an end insulating pattern”. One of the two instances should be changed to match the other instance so that consistent terminology is used. Note that the specification refers to “end insulation pattern” three times (in paragraphs 98, 117, and 169) and “end insulating pattern” ten times (in paragraphs 99–101, 138–139, 143, and 146).
Claim 14 is objected to because of the following informality: the 4th line refers to “the end insulation pattern”, which was introduced in the 2nd line as “an end insulating pattern”. One of the two instances should be changed to match the other instance so that consistent terminology is used.
Claim 17 is objected to because of the following informality: the 2nd line refers to “the lowest of the branch portions”, which should be amended to say “a lowest …” because this item is being introduced for the first time.
Claim 19 is objected to because of the following informality: under “each of the first electrode layers including …”, the word “are” on the first line of the 7th page of the claims (applicant’s page 58) should be deleted in “a first front end and a first back end spaced apart from each other in a third direction D3”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1–6, 9, and 19 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by patent application publication US 2020/0365616 A1 by Baek (“Baek’616” hereinafter).
Regarding claim 1, Baek’616 teaches:
A three-dimensional semiconductor memory device (FIGS. 4–5 and 6A–6D, “three-dimensional semiconductor memory device” ¶[0055]) comprising:
a substrate 100 (“horizontal layer 100” ¶[0060]) including a cell array region CAR and a connection region CNR side by side in a first direction D1 (see FIGS. 5 and 6A, “The horizontal layer 100 may include the cell array region CAR and the connection region CNR” ¶[0060]); and
a stack structure CST (see FIGS. 4 and 6A, “cell electrode structure CST” ¶[0042]) including electrode layers CGE (“cell gate electrodes CGE” ¶[0045]) and inter-electrode insulating layers (“intermediate dielectric layers ILDb” ¶[0081]) alternately stacked in a second direction D3 (“The cell electrode structure CST may include cell gate electrodes CGE and intermediate dielectric layers ILDb that are vertically and alternately stacked” ¶[0081]), the second direction D3 perpendicular to the substrate 100, the electrode layers CGE including first electrode layers (odd-numbered electrode layers CGE if numbered from 1 to N from bottom to top) and second electrode layers (even-numbered electrode layers CGE if numbered from 1 to N from bottom to top) alternately stacked,
each of the first electrode layers (odd-numbered electrode layers CGE) including
a first connection portion ECP (“connection portion ECP” ¶[0046]) in the cell array region CAR (as shown in FIG. 4, the connection portion ECP is continuous with the “electrode portions EP” that extend from the cell array region CAR, so the connection portion ECP may be said to extend into the cell array region CAR); and
a first front end FE1 and a first back end BE1 (see examiner’s annotations in FIG. 4) spaced apart from each other in a third direction D2 (as shown in FIG. 4, each odd-numbered electrode layer CGE has two line portions LP spaced apart from each other in the D2 direction, and the examiner has labeled FE1 as the nearest/foreground line portion LP, and BE1 as the farthest/background line portion LP), the third direction D2 intersecting the first D1 and second D3 directions, in the connection region CNR and positioned at a same level (i.e., each electrode CGE has, in a single horizontal plane, the electrode portion EP itself and two line portions LP),
the first front end FE1 and the first back end BE1 connected to the first connection portion ECP,
the first front end FE1 having a first protrusion PAD (“pad portion PAD” ¶[0049]) protruding toward the first back end BE1 (as shown in FIG. 4), and
the first protrusions PAD of the first front ends FE1 not overlapping the second electrode layers (even-numbered electrode layers CGE; i.e., as shown in FIG. 4, the pad portions PAD of one electrode layer CGE do not overlap in the vertical D3 direction with any part of any other electrode layer CGE because of the way the pad portions are stepped in the D1 direction).
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Regarding claim 2, Baek’616 teaches:
The three-dimensional semiconductor memory device (FIGS. 4–5 and 6A–6D) of claim 1, wherein each of the second electrode layers (even-numbered electrode layers CGE) includes:
a second connection portion ECP in the cell array region CAR (as shown in FIG. 4, the connection portion ECP is continuous with the “electrode portions EP” that extend from the cell array region CAR, so the connection portion ECP may be said to extend into the cell array region CAR); and
a second front end FE2 and a second back end BE2 (see examiner’s annotations in FIG. 4) spaced apart from each other in the third direction D2 (as shown in FIG. 4, each even-numbered electrode layer CGE has two line portions LP spaced apart from each other in the D2 direction, and the examiner has labeled FE2 as the nearest/foreground line portion LP, and BE2 as the farthest/background line portion LP) in the connection region CNR and positioned at a same level (i.e., each electrode CGE has, in a single horizontal plane, the electrode portion EP itself and two line portions LP),
[wherein] the second front end FE2 and the second back end BE2 are connected to the second connection portion ECP,
the second back end BE2 has a second protrusion PAD protruding toward the second front end FE2, and
the second protrusions PAD of the second back ends BE2 do not overlap the first electrode layers (odd-numbered electrode layers CGE; i.e., as shown in FIG. 4, the pad portions PAD of one electrode layer CGE do not overlap in the vertical D3 direction with any part of any other electrode layer CGE because of the way the pad portions are stepped in the D1 direction).
Regarding claim 3, Baek’616 teaches:
The three-dimensional semiconductor memory device (FIGS. 4–5 and 6A–6D) of claim 2, wherein upper surfaces of the first front ends FE1 are exposed without being covered by the second front ends FE2 (i.e., the upper surfaces of the first protrusions PAD of the first front ends FE1 of the odd-numbered electrode layers CGE are exposed without being covered by the second front ends FE2 of the even-numbered electrode layers CGE, as shown in the annotated FIG. 4).
Regarding claim 4, Baek’616 teaches:
The three-dimensional semiconductor memory device of claim 2, wherein upper surfaces of the second back ends BE2 are exposed without being covered by the first back ends BE1 (i.e., the upper surfaces of the second protrusions PAD of the second back ends BE2 of the even-numbered electrode layers CGE are exposed without being covered by the first back ends BE1 of the odd-numbered electrode layers CGE, as shown in the annotated FIG. 4; assuming based on the “…” in FIG. 4 that the undrawn electrode layers CGE continue in the same upward staircase pattern in the D1 direction so that another, undrawn first back end BE1 is stacked above the second back end BE2 and offset in the D1 direction so as to expose the PAD of the second back end BE2 underneath).
Regarding claim 5, Baek’616 teaches:
The three-dimensional semiconductor memory device (FIGS. 4–5 and 6A–6D) of claim 2, wherein
the first front ends FE1 form a step shape in the first direction D1, and
the first back ends BE1 form a step shape in the first direction D1 (as shown in FIG. 4).
Regarding claim 6, Baek’616 teaches:
The three-dimensional semiconductor memory device (FIGS. 4–5 and 6A–6D) of claim 2, wherein
the second front ends FE2 form a step shape in the first direction D1, and
the second back ends BE2 form a step shape in the first direction D1 (as shown in FIG. 4).
Regarding claim 9, Baek’616 teaches:
The three-dimensional semiconductor memory device (FIGS. 4–5 and 6A–6D) of claim 1, further comprising upper conductive lines UST (see FIG. 4, “upper electrode structure UST” ¶[0047]) positioned on an uppermost second electrode layer (true, since UST is above all the electrode layers CGE) among the second electrode layers (even-numbered electrode layers CGE),
wherein each of the upper conductive lines UST has a line shape extending in the first direction D1 (e.g., each electrode portion EP of the erase gate electrodes EGE of the upper electrode structure UST has a line shape extending in the first direction D1), and the upper conductive lines UST are spaced apart from each other in the third direction D2 (e.g., the electrode portions EP of the erase gate electors EGE are space apart in the third direction D2), and
wherein ends PAD (“pad portions” ¶[0049]) of the upper conductive lines UST do not overlap the first protrusions PAD (i.e., the pad portions PAD of the upper conductive lines UST do not overlap with any of the pad portions PAD of the electrode layers CGE, as shown in the perspective view of FIG. 4 or the cross-sectional view of FIG. 6A).
Regarding claim 19, Baek’616 teaches:
A three-dimensional semiconductor memory device (FIGS. 4–5 and 6A–6D, “three-dimensional semiconductor memory device” ¶[0055]) comprising:
a peripheral circuit structure PS (“peripheral logic structure PS” ¶[0056]), and
a cell array structure CS (“cell array structure CS” ¶[0056]) on the peripheral circuit structure PS (“a cell array structure CS on the peripheral logic structure PS” ¶[0056]), the cell array structure CS including
a substrate 100 (“horizontal layer 100” ¶[0060]) including a cell array region CAR and a connection region CNR side by side in a first direction D1 (see FIGS. 5 and 6A, “The horizontal layer 100 may include the cell array region CAR and the connection region CNR” ¶[0060]);
a source structure SST on the substrate 100 (“a source structure SST on the horizontal layer 100” ¶[0062]);
a stack structure CST (see FIGS. 4 and 6A, “cell electrode structure CST” ¶[0042]) including electrode layers CGE (“cell gate electrodes CGE” ¶[0045]) and inter-electrode insulating layers (“intermediate dielectric layers ILDb” ¶[0081]) alternately stacked in a second direction D3 (“The cell electrode structure CST may include cell gate electrodes CGE and intermediate dielectric layers ILDb that are vertically and alternately stacked” ¶[0081]), the second direction D3 perpendicular to an upper surface of the source structure SST, the electrode layers CGE including first electrode layers (odd-numbered electrode layers CGE if numbered from 1 to N from bottom to top) and second electrode layers (even-numbered electrode layers CGE if numbered from 1 to N from bottom to top) alternately stacked;
vertical patterns VS penetrating the stack structure CST and the source structure SST on the cell array region CAR (“vertical semiconductor patterns VS that penetrate the electrode structure ST [examiner: including the source structure SST as shown in FIG. 6A] on the cell array region CAR” ¶[0059]); and
cell contacts PLG2 penetrating an end of the stack structure CST on the connection region CNR (see FIG. 6A, “on the connection region CNR, second contact plugs PLG2 may penetrate the upper planarized dielectric layer 130 and may be coupled to corresponding pad portions PAD of the cell gate electrodes CGE” ¶[0088]),
each of the first electrode layers (odd-numbered electrode layers CGE) including
a first connection portion ECP (“connection portion ECP” ¶[0046]) in the cell array region CAR (as shown in FIG. 4, the connection portion ECP is continuous with the “electrode portions EP” that extend from the cell array region CAR, so the connection portion ECP may be said to extend into the cell array region CAR); and
a first front end FE1 and a first back end BE1 (see examiner’s annotations in FIG. 4) are spaced apart from each other in a third direction D2 (as shown in FIG. 4, each odd-numbered electrode layer CGE has two line portions LP spaced apart from each other in the D2 direction, and the examiner has labeled FE1 as the nearest/foreground line portion LP, and BE1 as the farthest/background line portion LP), the third direction D2 crossing the first D1 and second D3 directions, in the connection region CNR and positioned at a same level (i.e., each electrode CGE has, in a single horizontal plane, the electrode portion EP itself and two line portions LP),
the first front end FE1 and the first back end BE1 connected to the first connection portion ECP,
the first front end FE1 having a first protrusion PAD (“pad portion PAD” ¶[0049]) protruding toward the first back end BE1 (as shown in FIG. 4),
the first protrusions PAD of the first front ends FE1 not overlapping the second electrode layers (even-numbered electrode layers CGE; i.e., as shown in FIG. 4, the pad portions PAD of one electrode layer CGE do not overlap in the vertical D3 direction with any part of any other electrode layer CGE because of the way the pad portions are stepped in the D1 direction),
each of the second electrode layers (even-numbered electrode layers CGE) including
a second connection portion ECP in the cell array region CAR (as shown in FIG. 4, the connection portion ECP is continuous with the “electrode portions EP” that extend from the cell array region CAR, so the connection portion ECP may be said to extend into the cell array region CAR); and
a second front end FE2 and a second back end BE2 (see examiner’s annotations in FIG. 4) spaced apart from each other in the third direction D2 (as shown in FIG. 4, each even-numbered electrode layer CGE has two line portions LP spaced apart from each other in the D2 direction, and the examiner has labeled FE2 as the nearest/foreground line portion LP, and BE2 as the farthest/background line portion LP) in the connection region CNR and positioned at a same level (i.e., each electrode CGE has, in a single horizontal plane, the electrode portion EP itself and two line portions LP),
the second front end FE2 and the second back end BE2 connected to the second connection portion ECP,
the second back end BE2 having a second protrusion PAD protruding toward the second front end FE2,
the second protrusions PAD of the second back ends BE2 not overlapping the first electrode layers (odd-numbered electrode layers CGE; i.e., as shown in FIG. 4, the pad portions PAD of one electrode layer CGE do not overlap in the vertical D3 direction with any part of any other electrode layer CGE because of the way the pad portions are stepped in the D1 direction), and
the cell contacts PLG2 including first cell contacts PLG2 passing through the first protrusions PAD (of the odd-numbered electrode layers CGE) and second cell contacts PLG2 passing through the second protrusions PAD (of the even-numbered electrode layers CGE).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Baek’616 in view of patent application publication US 2022/0254802 A1 by Kwon et al. (from the IDS, “Kwon” hereinafter).
Regarding claim 20, Baek’616 teaches:
a semiconductor device (FIGS. 4–5 and 6A–6D, “three-dimensional semiconductor memory device” ¶[0055]) comprising
a peripheral circuit structure PS (“peripheral logic structure PS” ¶[0056]), and
a cell array structure CS (“cell array structure CS” ¶[0056]) on the peripheral circuit structure PS (“a cell array structure CS on the peripheral logic structure PS” ¶[0056]),
the cell array structure CS including
a substrate 100 (“horizontal layer 100” ¶[0060]) including
a cell array region CAR, and
a connection region CNR side by side in a first direction D1 (see FIGS. 5 and 6A, “The horizontal layer 100 may include the cell array region CAR and the connection region CNR” ¶[0060]), and a stack structure CST (see FIGS. 4 and 6A, “cell electrode structure CST” ¶[0042]) including
electrode layers CGE (“cell gate electrodes CGE” ¶[0045]) and inter-electrode insulating layers (“intermediate dielectric layers ILDb” ¶[0081]) alternately stacked in a second direction D3 (“The cell electrode structure CST may include cell gate electrodes CGE and intermediate dielectric layers ILDb that are vertically and alternately stacked” ¶[0081]), the second direction D3 perpendicular to the substrate 100, the electrode layers CGE including first electrode layers (odd-numbered electrode layers CGE if numbered from 1 to N from bottom to top) and second electrode layers (even-numbered electrode layers CGE if numbered from 1 to N from bottom to top) alternately stacked,
each of the first electrode layers (odd-numbered electrode layers CGE) including a first connection portion ECP (“connection portion ECP” ¶[0046]) in the cell array region CAR (as shown in FIG. 4, the connection portion ECP is continuous with the “electrode portions EP” that extend from the cell array region CAR, so the connection portion ECP may be said to extend into the cell array region CAR) and a first front end FE1 and a first back end BE1 (see examiner’s annotations in FIG. 4) spaced apart from each other in a third direction D2 (as shown in FIG. 4, each odd-numbered electrode layer CGE has two line portions LP spaced apart from each other in the D2 direction, and the examiner has labeled FE1 as the nearest/foreground line portion LP, and BE1 as the farthest/background line portion LP) crossing the first D1 and second D3 directions in the connection region CNR and positioned at a same level (i.e., each electrode CGE has, in a single horizontal plane, the electrode portion EP itself and two line portions LP),
the first front end FE1 and the first back end BE1 connected to the first connection portion ECP,
the first front end FE1 having a first protrusion PAD (“pad portion PAD” ¶[0049]) protruding toward the first back end BE1 (as shown in FIG. 4), and
the first protrusions PAD of the first front ends FE1 not overlapping the second electrode layers (even-numbered electrode layers CGE; i.e., as shown in FIG. 4, the pad portions PAD of one electrode layer CGE do not overlap in the vertical D3 direction with any part of any other electrode layer CGE because of the way the pad portions are stepped in the D1 direction).
However, Baek’616 fails to teach that the semiconductor device (FIGS. 4–5 and 6A–6D, “three-dimensional semiconductor memory device” ¶[0055]) is part of an electronic system;
that the semiconductor device further comprises an input/output pad electrically connected to the peripheral circuit structure PS; and
that the electronic system further comprises a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device.
Kwon teaches that a similar semiconductor device (FIGS. 5 and 6A–6B, “a three-dimensional (3D) semiconductor memory device” ¶[0004], corresponding to the semiconductor device 1100 of FIG. 1) is part of an electronic system 1000 (FIG. 1 shows an electronic system 1000 including a semiconductor device 1100).
Kwon’s semiconductor device 1100 further comprises an input/output pad 1101 (FIG. 1) electrically connected to the peripheral circuit structure 1130 (“The input/output pad 1101 may be electrically connected to the logic circuit 1130”; and “The lower-level layer PS [examiner: of FIG. 6A] may include a peripheral circuit including the decoder circuit, the page buffer, and the logic circuit” ¶[0054]).
Kwon’s electronic system 1000 further comprises a controller 1200 electrically connected to the semiconductor device 1100 through the input/output pad 1101 and configured to control the semiconductor device 1100 (“a controller electrically connected to the semiconductor device through the input/output pad and configured to control the semiconductor device” ¶[0008]; “an electronic system 1000 according to some example embodiments of the inventive concepts may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100” ¶[0022]; “The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. The electronic system 1000 may include a plurality of the semiconductor devices 1100 in some example embodiments, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100” ¶[0030]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the 3D semiconductor memory device from Baek’616 (FIGS. 4–5 and 6A–6D) with a controller to control the 3D semiconductor memory device through electrical connection to an input/output pad of the 3D semiconductor memory device in the same way as outlined schematically in Kwon’s FIG. 1. In combination, each element merely performs the same function as it does separately (see MPEP § 2103, Rationale A). The “semiconductor device” in both Baek’616 and Kwon is a 3D semiconductor memory device. The combination of Baek’616 and Kwon would pair a controller (from Kwon) with a 3D semiconductor memory device in the same way that Kwon has already paired a controller with a 3D semiconductor memory device through an input/output pad.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Baek’616 does not include
“an end insulating pattern between the second front ends and the second back ends on the connection region,
wherein the end insulation pattern includes:
a pillar portion extending in the second direction perpendicular to an upper surface of the substrate; and
branch portions protruding from a side surface of the pillar portion to the second front ends and the second back ends.”
That is, Baek’616 shows in FIGS. 5 and 6C that there are lower mold patterns LMP between the second front ends FE2 and the second back ends BE2 (see annotated FIG. 4 and compare to FIGS. 5 and 6C). These lower mold patterns LMP are analogous to the branch portions of the end insulating pattern of the present claim. However, Baek’616 does not have a pillar portion extending vertically (in the D3 direction) connecting the separate lower mold patterns LMP such that the lower mold patterns LMP protrude from a side surface of the pillar portion as required by the present claim.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 8 would be allowable at least for the reason that it depends on claim 7, which includes allowable subject matter as described above.
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Baek’616 does not teach that
“the upper conductive lines include first to sixth upper conductive lines sequentially in the third direction, and
the three-dimensional semiconductor memory device further includes:
a first upper separation pattern interposed between the first upper conductive line and the second upper conductive line and having a zigzag line shape in the first direction; and
a second upper separation pattern interposed between the third upper conductive line and the fourth upper conductive line and having a linear line shape in the first direction.”
Related prior art by Ryu et al. (from the IDS, patent application publication US 2021/0288054 A1, “Ryu” hereinafter) teaches in FIG. 1 that “the string selection line isolation layer 160 may have a zigzag pattern, and may extend in the first horizontal direction D1” ¶[0034], analogous to the first upper separation pattern of the present claim. The isolation insulating layer WLC has a linear line shape in the first direction D1, analogous to the second upper separation pattern of the present claim. However, Ryu’s FIG. 1 does not show first through sixth upper conductive lines.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 11 would be allowable at least for the reason that it depends on claim 10, which includes allowable subject matter as described above.
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Baek’616 does not teach that
“the substrate has a plurality of block regions arranged side by side in the third direction,
each of the block regions has a first width in the third direction, and
the first connection portion has the first width in the third direction.”
FIG. 1 of Baek’616 shows a plurality of block regions BLK0 to BLKn arranged side by side in the first direction D1, and each block region appears to have the same width in the D1 direction, which could be called a first width. Paragraph [0028] states that “Each of the memory blocks BLK0 to BLKn may include a memory cell array having a three-dimensional structure”. The cell array structure CS and peripheral logic structure PS of FIG. 1 correspond to the same labeled structures in the cross-sectional view of FIG. 6A. FIGS. 4 and 5 show that the first connection portion ECP has a width in the D2 direction (equivalent to the overall width in the D2 direction of the electrode structure ST in FIG. 5), so the width of the first connection portion ECP is not measured in the D1 direction (i.e., in the same direction in which the block regions BLK0 to BLKn are arranged side by side in FIG. 1) as required by the present claim.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Baek’616 does not teach that
“when viewed in a plan view, a side surface of the first protrusion of a lowest first electrode layer among the first electrode layers that meets an inner sidewall of the lowest first electrode layer is rounded.”
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Baek’616 does not include
“the end insulation pattern includes:
a pillar portion extending in the second direction perpendicular to an upper surface of the substrate; and
branch portions protruding from a side surface of the pillar portion toward the first front ends and the first back ends.”
That is, Baek’616 shows in FIGS. 5 and 6C that there are lower mold patterns LMP between the first front ends FE1 and the first back ends BE1 (see annotated FIG. 4 and compare to FIGS. 5 and 6C). These lower mold patterns LMP are analogous to the branch portions of the end insulating pattern of the present claim. However, Baek’616 does not have a pillar portion extending vertically (in the D3 direction) connecting the separate lower mold patterns LMP such that the lower mold patterns LMP protrude from a side surface of the pillar portion as required by the present claim.
Claims 15–17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 15–17 would be allowable at least for the reason that they depend on claim 14, which includes allowable subject matter as described above.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The closest prior art of Baek’616 does not teach that
“the first front end has a first width in the third direction, and
the first back end has a second width smaller than the first width in the third direction.”
That is, FIG. 4 of Baek’616, as annotated by the examiner, shows that the width of the first front end FE1 and the width of the first back end BE1 in the third direction D2 are equivalent to each other, both being the width of the pad portions PAD of the first front/back ends FE1/BE1. In other words, FIG. 4 does not satisfy the limitations of the present claim because for each electrode layer CGE, the two ends (i.e., the two line portions LP and two pad portions PAD) are symmetric on either side in the D2 direction, whereas the present claim would require the two ends to be asymmetric with the end on the negative-D2 side having a different width from the end on the positive-D2 side.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2021/0151462 A1 (from the IDS)—see FIGS. 2, 4, and 5; the pad regions PAD are analogous to the first/second protrusions of the present application
US 10,991,717 B2 (from the IDS)—see FIGS. 1 and 4–6; the pad patterns 180c are analogous to the first/second protrusions of the present application
US 2021/0193681 A1 (from the IDS)—see FIG. 10; the lower pads 51P are analogous to the first/second protrusions of the present application
US 2020/0402996 A1—see FIG. 10; the pad patterns 230a are analogous to the first/second protrusions of the present application
US 2020/0388624 A1—see FIGS. 52, 56, and 60
US 2020/0194373 A1—see FIG. 29; upper pads 71P and 72P; lower pad 62P
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam J Mott whose telephone number is (571)272-2367. The examiner can normally be reached Mon-Fri 8:30AM-5:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.J.M./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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