DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statements (IDS) filed on 11 October 2023, 28 October 2025 and 4 December 2025. The references cited on the PTOL 1449 forms have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the following limitations with respect to the first MISFET:
“a first MISFET formed on the upper surface of the semiconductor substrate”
“s substrate region … formed in the semiconductor substrate”
“a first source region … of the first MISFET”
“a first drain region … of the first MISFET”
“the first source region and the first drain region being formed in the substrate region”
“a first gate electrode of the first MISFET formed on the semiconductor substrate”
There is a conflict based on which elements are formed in and which are formed on the semiconductor substrate or substrate region that is in the semiconductor substrate.
A MISFET comprises many structural features including a source region, drain region, channel region, gate insulator and gate electrode. Of these, the source, drain and channel regions are formed in the semiconductor while the gate insulator and gate electrode are formed on the semiconductor.
Based on the claim language, it’s unclear as to how the first MISFET is to be formed on the semiconductor while at the same time parts comprised by the first MISFET are formed in the semiconductor.
Claim 1 also recites “a first source region of a second conductivity type opposite the first conductivity type of the first MISFET” which is not clear and concise based on the compounded overuse of the terms “of” in the claim.
It appears that perhaps the paragraph that includes the recitation was intended to mean:
wherein the first MISFET comprises a first source region and a first drain region;
wherein the first source region and the first drain region each comprise a second conductivity type opposite the first conductivity type;
Based on the claim language, it’s unclear as to the meaning of opposite the first conductivity type of the first MISFET.
Claims 2-20 include the limitations of claim 1.
Claim 15 recites the limitation “the second voltage” at line 5. There is insufficient antecedent basis for this limitation in the claim. Perhaps, this limitation was intended for the recitation to refer to the second MISFET.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 8, 11, 13-17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fuji et al. (U.S. Patent Application Publication 2018/0342577).
Referring to Claim 1, Fuji teaches in Fig. 3-7 for example, a semiconductor device comprising: a semiconductor substrate (SUB) having an upper surface; a substrate region (HWL) of a first conductivity type formed in the semiconductor substrate (SUB); a first MISFET (par. 53; pLDMOS) formed on the upper surface of the semiconductor substrate (SUB); a first source region (SC) of a second conductivity type opposite the first conductivity type of the first MISFET (pLDMOS) and a first drain region (DC) of the second conductivity type of the first MISFET (pLDMOS), the first source region (SC) and the first drain region (DC) being formed in the substrate region (HWL) and spaced apart from each other; a first gate electrode (GE) of the first MISFET (pLDMOS) formed on the semiconductor substrate (SUB) between the first source region (SC) and the first drain region (DC) via a first gate dielectric film (GI); a first semiconductor region (NWL) of the first conductivity type formed in the substrate region (HWL) so as to partially overlap with the first gate electrode (GE) in plan view, the first semiconductor region (NWL) having an impurity concentration (n) higher than an impurity concentration (n-) of the substrate region (HWL); a second semiconductor region (WC) of the first conductivity type formed in the substrate region (HWL) so as not to overlap with the first gate electrode (GE) in plan view and so as to be adjacent to the first source region (SC), the second semiconductor region (WC) having an impurity concentration (n+) higher than the impurity concentration (n) of the first semiconductor region (NWL); and a third semiconductor region (DFT) of the second conductivity type formed in the substrate region (HWL) so as to partially overlap with the first gate electrode (GE) in plan view and electrically connected to the first drain region (DC), the third semiconductor region (DFT) having an impurity concentration (p-) lower than an impurity concentration (p+) of the first drain region (DC), wherein the first gate electrode (GE) extends in a first direction (vertically in Fig. 3) along the upper surface of the semiconductor substrate (SUB), wherein the first semiconductor region (NWL) extends in the first direction (vertically in Fig. 3; in/out of page in Fig. 4 and 5) so as to cover a bottom surface of the first source region (SC) and a bottom surface of the second semiconductor region (WC) (see Fig. 4-5), wherein the semiconductor substrate (SUB) includes a first region (at line V-V of Fig. 3 and 5) and a second region (at line IV-IV of Fig. 3 and 4) alternately disposed in the first direction (vertically in Fig. 3), wherein a width of the first semiconductor region (NWL) overlapping with the first gate electrode (GE) in a second direction (horizontally in Fig. 3 and 4) in the second region (at line IV-IV of Fig. 3 and 4) is smaller than a width of the first semiconductor region (NWL) overlapping with the first gate electrode (GE) in the second direction (horizontally in Fig. 3 and 5) in the first region (at line V-V of Fig. 3 and 5), and wherein the second direction (horizontally in Fig. 3-5) is orthogonal to the first direction (vertically in Fig. 3; in/out of page in Fig. 4 and 5) and along the upper surface of the semiconductor substrate (SUB).
Referring to Claim 2, Fuji further teaches wherein a part of the first semiconductor region (NWL) is located under the first gate electrode (GE) in cross sectional view orthogonal to the first direction (vertically in Fig. 3) in the first region (at line V-V) while the first semiconductor region (NWL) is not located under the first gate electrode (GE) in cross sectional view orthogonal to the first direction in the second region (at line IV-IV) (Fig. 3-5).
Referring to Claim 3, Fuji further teaches in Fig. 4 and 5, an interlayer dielectric film (IS) formed on the semiconductor substrate (SUB) so as to cover the first gate electrode (GE); and a plurality of contact plugs (PL) buried in the interlayer dielectric film (IS), wherein a first contact plug (CN2) of the plurality of contact plugs (PL) is disposed on the first source region (SC) and electrically connected to the first source region (SC),
wherein a second contact plug (CN1) of the plurality of contact plugs (PL) is disposed on the second semiconductor region (WC) and electrically connected to the second semiconductor region (WC).
Referring to Claim 4, Fuji further teaches in Fig. 4 and 5, a first wiring (INC) formed on the interlayer dielectric film (IS), wherein the first contact plug (CN2) and the second contact plug (CN1) are electrically connected to the first wiring (INC).
Referring to Claim 5, Fuji further teaches in Fig. 4 and 5 (par. 73), the required structure capable to provide the function of wherein a potential supplied from the first contact plug (CN2) to the first source region (SC) and a potential supplied from the second contact plug (CN1) to the second semiconductor region (WC) are the same as each other. It is noted that recitations of a supplying a potential (or in the past tense of a potential having been applied) are not structural but rather describes a function.
Referring to Claim 7, Fuji further teaches wherein in plan view, a location of an end portion facing the third semiconductor region (DFT) of the first semiconductor region (NWL) in the second region (at line IV-IV; Fig. 3 and 4) is retracted away from the third semiconductor region (DFT) than the location of the end portion facing the third semiconductor region (DFT) of the first semiconductor region (NWL) in the first region (at line V-V; Fig. 3 and 5).
Referring to Claim 8, Fuji further teaches wherein each of the first source region (SC) and the second semiconductor region (WC) extends in the first direction, and wherein the first source region (SC) and the second semiconductor region (WC) are adjacent to each other in the second direction.
Referring to Claim 11, Fuji further teaches wherein a dimension (WD) of the first region (at line V-V) in the first direction is smaller than a dimension (WW) of the second region (at line IV-IV) in the first direction (Fig. 6; par. 72).
Referring to Claim 13, Fuji further teaches in Fig. 3-5 wherein in plan view, a location of an end portion facing the first semiconductor region (NWL) of the third semiconductor region (DFT) in the second region (at line IV-IV) is retracted away from the first semiconductor region (NWL) than the location of the end portion facing the first semiconductor region (NWL) of the third semiconductor region (DFT) in the first region (at line V-V).
Referring to Claim 14, Fuji further teaches wherein the first MISFET is an LDMOSFET (par. 40).
Referring to Claim 15, Fuji further teaches in Fig. 2 and 23-25, a second MISFET (nLDMOS) formed on the upper surface of the semiconductor substrate (SUB), wherein a threshold voltage of the first MISFET (pLDMOS) and a threshold voltage of the second MISFET (nLDMOS) are different from each other.
Referring to Claim 16, Fuji further teaches a second source region (SC) of the second conductivity type of the second MISFET (nLDMOS) and a second drain region (DC) of the second conductivity type of the second MISFET (nLDMOS), the second source region (SC) and the second drain region (DC) being formed in the substrate region (HWL) and spaced apart from each other; a second gate electrode (GE) of the second MISFET (nLDMOS) formed on the semiconductor substrate (SUB) between the second source region (SC) and the second drain region (DC) via a second gate dielectric film (GI); a fourth semiconductor region (PWL) of the first conductivity type (p) formed in the substrate region (HWL) so as to partially overlap with the second gate electrode (GE) in plan view, the fourth semiconductor region (PWL) having an impurity concentration (p) higher than the impurity concentration (p-) of the substrate region (HWL); a fifth semiconductor region (WC) of the first conductivity type (p) formed in the substrate region (HWL) so as not to overlap with the second gate electrode (GE) in plan view and so as to be adjacent to the second source region (SC), the fifth semiconductor region (WC) having an impurity concentration (p+) higher than the impurity concentration (p) of the fourth semiconductor region (PWL); and a sixth semiconductor region (DFT) of the second conductivity type (n) formed in the substrate region (HWL) so as to partially overlap with the second gate electrode (GE) in plan view and electrically connected to the second drain region (DC), the sixth semiconductor region (DFT) having an impurity concentration (n-) lower than an impurity concentration (n+) of the second drain region (DC), wherein the second gate electrode (GE) extends in the first direction, and wherein the fourth semiconductor region (PWL) extends in the first direction while overlapping with the second gate electrode (GE) with a constant width in plan view so as to cover a bottom surface of the second source region (SC) and a bottom surface of the fifth semiconductor region (WC) (Fig. 2 and par. 38-41 and 52 as well as par. 111-11 and Fig. 24-25).
Referring to Claim 17, Fuji further teaches wherein the first conductivity type is a p-type, wherein the second conductivity type is an n-type, and wherein the threshold voltage of the second MISFET (nLDMOS) is lower than the threshold voltage of the first MISFET (pLDMOS) (par. 38-41).
Referring to Claim 19, Fuji further teaches wherein in the second direction, a smallest distance between the first semiconductor region (NWL) and the third semiconductor region (right edge of DFT) in the second region (at line IV-IV) is greater than a smallest distance between the first semiconductor region (NWL) and the third semiconductor region (right edge of DFT) in the first region (at line V-V).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Fuji et al. (U.S. Patent Application Publication 2018/0342577) in view of Yamada (U.S. Patent Application Publication 2014/0035031)
Referring to Claim 9, Fuji teaches the limitations of claim 1, but does not explicitly state wherein the first source region (SC) and the second semiconductor region (WC) are alternately disposed in the first direction.
In the same field of endeavor, Yamada teaches in Fig. 1 and 2A-2B a LDMOS transistor wherein the first source region (24) and the second semiconductor region (26) are alternately disposed in the first direction.
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to alternately arrange the first source and second semiconductor regions of Fuji as taught by Yamada in order to improve the amount of breakdown voltage while not reducing the area of the source thereby suppressing the increase in on resistance (par. 38-43).
Referring to Claim 10, as modified above, Fuji in view of Yamada further teach wherein the first region (at line V-V) overlaps with the second semiconductor region (WC) in plan view, and wherein the second region (at line IV-IV) overlaps with the first source region (SC) in plan view.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Fuji et al. (U.S. Patent Application Publication 2018/0342577) in view of in view of Mori (U.S. Patent Application Publication 2017/0250259)
Referring to Claim 18, Fuji teaches the limitations of claim 1 wherein the semiconductor substrate (SUB) includes: a substrate (SB) but does not explicitly state wherein the semiconductor substrate (SUB) includes: an epitaxial semiconductor layer formed on the substrate, wherein the epitaxial semiconductor layer is the substrate region (HWL).
In the same field of endeavor, Mori teaches wherein the semiconductor substrate (S1) includes: a substrate (S); and an epitaxial semiconductor layer (PEP) formed on the substrate (S), wherein the epitaxial semiconductor layer (PEP) is the substrate region (PWL) (par. 61-66).
It would have been obvious to one having ordinary skill in the art before the invention was effectively filed to form the substrate region of Fuji as an epitaxial layer as taught by Mori based on its well-known suitability in the art for providing semiconductor layers and regions therein of an LDMOS transistor.
Allowable Subject Matter
Claims 6, 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 6, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein in the first region, an upper part of the substrate region located under the first gate electrode and an upper part of the first semiconductor region located under the first gate electrode are channel forming regions of the first MISFET, and wherein in the second region, the upper part of the substrate region located under the first gate electrode is the channel forming region of the first MISFET in combination with all of the limitations of Claim 1.
Regarding Claim 12, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein in the first region, a dimension in the first direction of a portion where the first semiconductor region overlaps with the first gate electrode in plan view is the smallest at an end portion facing the third semiconductor region and gradually increases as the distance from the third semiconductor region increases in combination with all of the limitations of Claim 1 and 12.
Regarding Claim 20, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor device wherein in the second direction, an end portion of the first semiconductor region closest to the third semiconductor region in the second region is exposed from the first gate electrode in combination with all of the limitations of Claim 1 and 20.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896