Prosecution Insights
Last updated: May 29, 2026
Application No. 18/484,982

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Oct 11, 2023
Priority
Nov 21, 2022 — JP 2022-185389
Examiner
ESIABA, NKECHINYERE OTUOMASIRICH
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Renesas Electronics Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
10m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
7 granted / 9 resolved
+9.8% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
28 currently pending
Career history
45
Total Applications
across all art units

Statute-Specific Performance

§103
80.5%
+40.5% vs TC avg
§102
13.8%
-26.2% vs TC avg
§112
4.6%
-35.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 9 resolved cases

Office Action

§103
DETAILED ACTION This Notice is responsive to communication filed on 10/11/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/11/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election without traverse of Species 1, reading on Fig. 2 in the reply filed on 03/25/2026 is acknowledged. Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/25/2026. Claim Objections Claim 1 is objected to because of the following informalities: the limitation “and the following Formula 1 is satisfied. L1 > T1 × 2.45 - 4.61 [Symbol font/0x6D]m … Formula 1”. It appears the formula should be included in the text of claim 1, before and not after the period punctuation mark. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lei et al. (US 20140117533) and further in view of Usami (US 20190198468) and Yotsuda (US 20230282686). Regarding claim 1, Lei teaches a semiconductor device comprising: a semiconductor substrate Fig. 11: 100; a first insulation film (para. 0014 “insulating material not shown”) formed on the semiconductor substrate Fig. 11: 100; a pad formed Fig. 11: 106 on the first insulation film; a second insulation film Fig. 11: 110 formed on the first insulation film so as to cover the pad Fig. 11: 106, the second insulation film Fig. 11: 110 including a first opening Fig. 6: 118 partially exposing the pad Fig. 11: 106; a third insulation film Fig. 11: 112 formed on the second insulation film Fig. 11: 110, the third insulation film Fig. 11: 112 including a second opening Fig. 6: 118 partially exposing the pad Fig. 11: 106; and a metal film Fig. 11: 128+134+138 (para. 0038 teaches 138 film) formed on the pad Fig. 11: 106 exposed from the second opening Fig. 6: 118, wherein the first opening Fig. 6: 118 is included in the pad Fig. 11: 106 in plan view, wherein the second opening Fig. 6: 118 is included in the first opening Fig. 6: 118 in plan view (both openings, in this case shown as Fig. 6: 118, are included on the top portion of the pad 106), wherein an inner wall of the first opening Fig. 6: 118 of the second insulation film Fig. 11: 110 is covered with the third insulation film Fig. 11: 112 (shown in Fig. 11), wherein the metal film Fig. 11: 128+134+138 includes a nickel plating film Fig. 11: 128 (para. 27) in contact with the pad Fig. 11: 106. But Lei fails to explicitly teach wherein the second insulation film is made of silicon oxide, wherein the third insulation film is made of silicon nitride or silicon oxynitride, and wherein when a distance from an outer circumference of the pad to the inner wall of the first opening is L1 ([Symbol font/0x6D]m) while a thickness of the nickel plating film is T1 ([Symbol font/0x6D]m), T1 is equal to or greater than 2.5 [Symbol font/0x6D]m, and the following Formula 1 is satisfied; L1 > T1 × 2.45 - 4.61 [Symbol font/0x6D]m … Formula 1. However, Usami teaches wherein the second insulation film Fig. 2: IF1 is made of silicon oxide, wherein the third insulation film Fig. 2: IF1 is made of silicon nitride or silicon oxynitride. In para. 0076, Usami teaches the insulating layer IF1 can be a laminated first silicon oxide film and then a silicon nitride film formed over the silicon oxide film. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lei and Usami for the purpose of utilizing a silicon oxide/silicon nitride insulating film of 500 nm – 800 nm thickness, which is a material that is highly resistant to moisture, for preventing moisture from entering the pad (para. 0052) and allowing a route of leakage between rewiring layers to be separated by the insulating film (para. 0112). Also, Yotsuda teaches wherein when a distance from an outer circumference of the pad Fig. 1: 18 to the inner wall of the first opening Fig. 4B: 43 is L1 ([Symbol font/0x6D]m) (see Fig. 1: 53/55) while a thickness of the nickel plating film Fig. 1: 20 is T1 ([Symbol font/0x6D]m), T1 is equal to or greater than 2.5 [Symbol font/0x6D]m (para. 0042 teaches 20a = 50 nm - 200 nm, and 20b = 1 µm-6 µm, which includes the range ≥ 2.5 µm) and the following Formula 1 is satisfied; L1 > T1 × 2.45 - 4.61 [Symbol font/0x6D]m … Formula 1. In this case, using about 2.5 µm as the thickness of the nickel plating film as taught by Yotsuda, and including the distance between Fig. 1: 53 to 55, which is given by L3 minus L2 (para. 0045; i.e. L3 = 5 µm, L2 = 3µm; L3-L2 = 2µm), the formula above is satisfied. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lei and Yotsuda for the purpose of improving breakdown voltage (para. 0028, 0058). Regarding claim 2, Yotsuda teaches wherein the thickness of T1 of the nickel plating film Fig. 1: 20 is equal to or greater than 3 µm (para. 0042 teaches a range including 6 µm). Regarding claim 4, Lei teaches the semiconductor device according to claim 1, wherein the metal film Fig. 11: 128+134+138 includes a gold plating film Fig. 11: 134 formed on the nickel plating film Fig. 11: 128 (para. 0032). Regarding claim 5, Lei teaches the semiconductor device according to claim 1, wherein the metal film Fig. 11: 128+134+138 includes: a palladium plating film 138 (para. 0032, not pictured) formed on the nickel plating film Fig. 11: 128; and a gold plating film Fig. 11: 134 formed on the palladium plating film 138 (para. 0032, not pictured). Regarding claim 6, Lei teaches the semiconductor device according to claim 1, wherein the pad Fig. 11: 106 includes an Al-containing conductive film mainly made of aluminum (para. 0015). Regarding claim 7, Lei teaches the semiconductor device according to claim 1, wherein the thickness of the nickel plating film Fig. 11: 128 is equal to or smaller than a sum of a thickness of the second insulation film Fig. 11: 110 and a thickness of the third insulation film Fig. 11: 112. Para. 0017 teaches a second insulation film thickness of 1.5µm; Para 0018 teaches a third insulation film thickness of 10µm; Para. 0027 teaches a nickel plating film thickness of 1µm, which is less than the sum of the second and third insulation films. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lei et al. (US 20140117533), Usami (US 20190198468) and Yotsuda (US 20230282686) as applied to claim 1 above, and further in view of Tonegawa et al. (US 20190067225). Regarding claim 3, although Lei, Usami, and Yotsuda teach the substantial elements of the claimed invention, they fail to explicitly teach the semiconductor device according to claim 1, wherein the nickel plating film is a nickel electroless plating film. However, Tonegawa teaches wherein the nickel plating film Fig. 7: PF1 is a nickel electroless plating film (para. 0004, 0063 teaches the electroless plating). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lei, Usami, Yotsuda and Tonegawa for the purpose of improving uniformity of the thickness of the conductive film/nickel plating film using a low sheet resistance material (para. 0064, 0067). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nkechinyere Esiaba/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 10, 2026
Read full office action

Prosecution Timeline

Oct 11, 2023
Application Filed
Apr 14, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12550491
DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME AND TILED DISPLAY DEVICE INCLUDING THE SAME
3y 2m to grant Granted Feb 10, 2026
Patent 12506102
FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH FACE MOUNTED PASSIVES AND METHOD OF MAKING THE SAME
3y 5m to grant Granted Dec 23, 2025
Patent 12489076
POWER MODULE FOR HIGH-FREQUENCY USE AND METHOD FOR MANUFACTURING THE SAME
3y 4m to grant Granted Dec 02, 2025
Patent 12457832
LIGHT EMITTING DEVICE AND DIFFUSION MEMBER USED THEREIN
2y 12m to grant Granted Oct 28, 2025
Patent 12309994
METHOD OF MANUFACTURING MEMORY DEVICE HAVING DOUBLE SIDED CAPACITOR
3y 2m to grant Granted May 20, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
99%
With Interview (+25.0%)
3y 5m (~10m remaining)
Median Time to Grant
Low
PTA Risk
Based on 9 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month