DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 3 and 18 are objected to because of the following informalities: the third limitation of claims 1 and 18 each recite “the material of the regions having… refractive index” which contains a typo for failing to include an article before ‘refractive index’; the third limitation of claims 1 and 18 each recite “the substrate” which contains a typo in failing to amend this to read ‘ the first semiconductor substrate’ in line with other instances of the phrase; and claim 3 recites ‘an refractive index’ which contains the wrong article. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0305206 A1 to Deneuville (hereinafter “Deneuville” – previously cited reference).
Regarding claim 1, Deneuville discloses a device for acquiring a 2D image and a depth image (claim 1), comprising:
a first sensor formed in and on a first semiconductor substrate, the first semiconductor substrate having a front face and a rear face (claim 1), the first sensor comprising a plurality of 2D image pixels, an interconnect stack located on the front face side of the first semiconductor substrate and in which electrical connection tracks and/or terminals are formed (claim 2), and regions of a material distinct from that of the first semiconductor substrate located in the interconnect stack in line with 2D image pixels (material layer of interconnect stack 110 in line with pixels P1; Fig. 1; paragraphs [0031], [0035]); and
adjoining the first sensor on the front face side of the first semiconductor substrate, a second sensor formed in and on a second semiconductor substrate and comprising a plurality of depth pixels located opposite the regions of the first sensor (claim 1);
wherein each region comprises a first portion extending into the interconnect stack from a first face of the interconnect stack facing the first semiconductor substrate and a second portion extending from a second face of the interconnect stack (material layer of interconnect stack 110 comprises first portion of amorphous silicon 50 region extending into first outer surface of stack 110 facing substrate 100 and second portion of amorphous silicon 50 region extending into second outer surface of stack facing second substrate 130; Fig. 1; paragraph [0038]) opposite the first semiconductor substrate, to the first portion, the first portion having, in top view, a smaller surface area than the second portion (first and second portions of region 50 may be defined such that the first has a smaller surface area than the second; Fig. 1), the material of the regions having, over a working wavelength range of the second sensor, a refractive index greater than or equal to that of the material of the substrate (material layer of interconnect stack 110 comprises amorphous silicon 50 having a refractive index at 940 nm higher than that of single-crystal silicon substrate 100; Fig. 1; paragraphs [0031], [0038]);
wherein the interconnect stack includes alternating dielectric and conductive layers coating sides of each region and electrically isolating each region from the electrical connection tracks and/or terminals (interconnect stack 110 formed of alternating dielectric and conductive layers coated on sides of regions 50 and electrically isolating each region 50 from electric connection tracks and/or terminals 111; Fig. 1; paragraph [0035]).
Weber fails to explicitly disclose the interconnect stack coating a top face of each region.
However, Weber already discloses in Fig. 2F an intermediate step where the alternating layers of the interconnect stack 110 is disposed on a top face of the region 50.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Weber in this manner to utilize a slightly altered shape of the region 50 in a manner that only requires a mere rearrangement of parts already disclosed by Weber for the potential purpose of providing continuous dielectric film that improves wafer-level planarity for higher quality bond to sensor C2, and extra dielectric thickness disposed upon region 50 can function with the anti-reflection stack 126, 128 to raise transmission into he underlying SPAD pixels.
Regarding claim 2, Deneuville discloses the device according to claim 1, wherein the material of the regions further has an absorption coefficient less than or equal to 10-3 μm-1 (material layer of interconnect stack 110 comprises amorphous silicon 50 which has an absorption coefficient in the range of between 10^2 and 10^4 cm^-1 at 940 nm; Fig. 1; paragraph [0038]).
Regarding claim 3, Deneuville discloses the device according to claim 1, wherein the material of the regions has an refractive index greater than or equal to 3.5 (material layer of interconnect stack 110 comprises amorphous silicon 50 having a refractive index at 940 nm of about 3.6; paragraphs [0031], [0038]).
Regarding claim 4, Deneuville discloses the device according to claim 1, wherein the material of the regions is amorphous silicon (material layer of interconnect stack 110 comprises amorphous silicon 50; paragraphs [0031], [0038]).
Regarding claim 5, Deneuville discloses the device according to claim 1, wherein the electrical connection tracks and/or terminals penetrate inside the first portion of each region (terminals 111 penetrate within material layer of interconnect stack 110; Fig. 1).
Regarding claim 6, Deneuville discloses the device according to claim 1, wherein each region is delimited laterally, over its entire periphery and height, by a dielectric material having a refractive index lower than that of the material of the region (stack 110 comprises dielectric material, e.g. silicon oxide, which has a refractive index lower than that of amorphous silicon 50; paragraphs [0035]-[0036]).
Regarding claim 7, Deneuville discloses the device according to claim 1, wherein each region extends over a thickness substantially equal to that of the interconnect stack and is flush with the face of the interconnect stack opposite the first semiconductor substrate (material layer of stack 110 having silicon 50 with equal thickness and flush with outer surfaces of stack 110 opposite substrate 100; Fig. 1).
Regarding claim 8, Deneuville discloses the device according to claim 1, wherein the first sensor is a color image sensor, each 2D image pixel comprising a color filter transmitting red, green or blue light (sensor C1 comprises color filter 118 transmitting red, green or blue light; paragraph [0043]).
Regarding claim 9, Deneuville discloses the device according to claim 8, wherein the regions are located solely in line with the 2D image pixels comprising the color filter transmitting blue light (material layer of interconnect stack 110 in line with pixels P1 having filter 118 transmitting blue light; Fig. 1; paragraphs [0031], [0035], [0043]).
Regarding claim 10, Deneuville discloses the device according to claim 8, wherein the regions are located in line with each 2D image pixel of the sensor (material layer of interconnect stack 110 in line with pixels P1; Fig. 1; paragraphs [0031], [0035]).
Regarding claim 11, Deneuville discloses the device according to claim 8, in which the pixels located in line with the regions are grouped in groups of four adjacent pixels (red, green, blue pixels P1 and pixel P2; Fig. 1; paragraphs [0043], [0046]).
Regarding claim 12, Deneuville discloses the device according to claim 11, wherein, for each group of four adjacent pixels, each region is common to all four pixels (material layer of interconnect stack 110 common to pixels P1, P2; Fig. 1; paragraphs [0043], [0046]).
Regarding claim 13, Deneuville discloses the device according to claim 1, further comprising, between each region of the first sensor and the corresponding depth pixel of the second sensor, alternating dielectric layers of distinct refractive indices, forming an anti-reflective stack for light rays passing through each region in a direction of said depth pixel (between material layer of interconnect stack 110 of the first sensor and the corresponding depth pixel of the second sensor, an alternation of dielectric layers having distinct refraction indices, forming an antireflection stack for light rays crossing said transmissive window towards said depth pixel; paragraph [0016]; claim 8).
Regarding claim 14, Deneuville discloses the device according to claim 1, in which the second sensor comprises, on the side facing the rear of the second semiconductor substrate, an interconnect stack in which electrical connection tracks and/or terminals are formed (claim 9).
Regarding claim 15, Deneuville discloses the device according to claim 1, in which each depth pixel of the second sensor comprises a SPAD-type photodiode (claim 10).
Regarding claim 16, Deneuville discloses the device according to claim 1, in which each depth pixel of the second sensor comprises several memory zones coupled to a same detection zone, and enables measurement of a phase shift between an amplitude-modulated light signal emitted by a light source of the device and a light signal received by a photodetection zone of the pixel, after reflection on a scene whose image is to be acquired (claim 11).
Regarding claim 17, Deneuville discloses the device according to claim 1, in which the first and second semiconductor substrates are made of monocrystalline silicon (single crystal substrates 100, 130; paragraphs [0031]-[0032]; claim 12).
Regarding claim 18, Deneuville discloses a method of manufacturing a device for acquiring a 2D image and a depth image (claim 1), the method comprising the following successive steps:
a) forming, in and on a first semiconductor substrate, a first sensor having a front face and a rear face (claim 1), the first sensor comprising a plurality of 2D image pixels, an interconnect stack located on the front face side of the first semiconductor substrate and in which electrical connection tracks and/or terminals are formed (claim 2), and regions of a material distinct from that of the semiconductor substrate located in the interconnect stack in line with 2D image pixels (material layer of interconnect stack 110 in line with pixels P1; Fig. 1; paragraphs [0031], [0035]); and
b) forming, in and on a second semiconductor substrate, a second sensor comprising a plurality of depth pixels located opposite the regions of the first sensor; and
c) joining the second sensor to the first sensor on the front face side of the first semiconductor substrate (claim 1), wherein each region comprises a first portion extending into the interconnect stack from a first face of the interconnect stack facing the first semiconductor substrate and a second portion extending (material layer of interconnect stack 110 comprises first portion of amorphous silicon 50 region extending into first outer surface of stack 110 facing substrate 100 and second portion of amorphous silicon 50 region extending into second outer surface of stack facing second substrate 130; Fig. 1; paragraph [0038]), from a second face of the interconnect stack opposite the first semiconductor substrate, to the first portion, the first portion having, in top view, a smaller surface area than the second portion (first and second portions of region 50 may be defined such that the first has a smaller surface area than the second; Fig. 1), the material of the regions having, over a working wavelength range of the second sensor, an refractive index greater than or equal to that of the material of the substrate (material layer of interconnect stack 110 comprises amorphous silicon 50 having a refractive index at 940 nm higher than that of single-crystal silicon substrate 100; Fig. 1; paragraphs [0031], [0038]);
wherein the interconnect stack includes alternating dielectric and conductive layers coating sides of each region and electrically isolating each region from the electrical connection tracks and/or terminals (interconnect stack 110 formed of alternating dielectric and conductive layers coated on sides of regions 50 and electrically isolating each region 50 from electric connection tracks and/or terminals 111; Fig. 1; paragraph [0035]).
Weber fails to explicitly disclose the interconnect stack coating a top face of each region.
However, Weber already discloses in Fig. 2F an intermediate step where the alternating layers of the interconnect stack 110 is disposed on a top face of the region 50.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Weber in this manner to utilize a slightly altered shape of the region 50 in a manner that only requires a mere rearrangement of parts already disclosed by Weber for the potential purpose of providing continuous dielectric film that improves wafer-level planarity for higher quality bond to sensor C2, and extra dielectric thickness disposed upon region 50 can function with the anti-reflection stack 126, 128 to raise transmission into he underlying SPAD pixels.
Regarding claim 19, Deneuville discloses the method according to claim 18, comprising the following steps: forming a first part of the interconnect stack; forming the first part of each region; forming a second portion of the interconnect stack; and forming the second part of each region (Figs. 2A-2J; paragraph [0063]).
Deneuville fails to disclose comprising the following successive steps: forming a first part of the interconnect stack; forming the first part of each region; forming a second portion of the interconnect stack; and forming the second part of each region.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the steps already disclosed by Deneuville to be in a particular successive order in order to potentially provide reduced manufacturing cost and process simplification.
Regarding claim 20, Deneuville discloses the method according to claim 19, in which the first and second parts of each region are formed after the interconnect stack has been completed (first and second portions of amorphous silicon 50 are formed after remainder of material layer of interconnect stack 110 is formed; Figs. 2A-2J; paragraph [0063]).
Response to Arguments
Applicant's arguments filed July 9, 2026 have been fully considered. Applicant presents substantive amendments to claims 1 and 18 and corresponding arguments. Specifically, Applicant asserts that amended claims 1 and 18 overcome the existing 35 USC 102 rejection. Examiner agrees, but has rejected these claims under 35 USC 103 as outlined above given, in part, the disclosure of Fig. 2F of Deneuville.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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