Prosecution Insights
Last updated: April 18, 2026
Application No. 18/485,181

DEVICE FOR ACQUIRING A 2D IMAGE AND A DEPTH IMAGE OF A SCENE

Non-Final OA §102§103§112
Filed
Oct 11, 2023
Examiner
DEGRASSE, IAN ISAAC
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
61%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
10 granted / 12 resolved
+15.3% vs TC avg
Minimal -22% lift
Without
With
+-22.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
54 currently pending
Career history
66
Total Applications
across all art units

Statute-Specific Performance

§103
51.7%
+11.7% vs TC avg
§102
34.8%
-5.2% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 12 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, claim 1 recites: “a first portion” and “a second portion” of the regions and then later refers to this as “the first part” and “the second part” of the regions (also contained in claims 5 and 18-20); “a second face” which is then repeated and thereby creates a lack of clarity; “a first semiconductor substrate” and “a second semiconductor substrate” are introduced and then “the substrate” is later referenced which creates a lack of clarity (also contained in claim 18); “an optical index” which is then repeated in claim 3 and compared to “a refractive index” in claim 6 which creates a lack of clarity in each claim. Claim 2 recites “the material of the regions further has an absorption coefficient less than or equal to 10^-3” but the absorption coefficient of the material of the regions is inherently wavelength-dependent and so claiming a general absorption coefficient value of 10-3 (without listing the proper units) is indefinite. Claims 6-7, 12 and 19-20 recite “the region” in singular form after having been introduced in plural form in claims 1 and 18 which creates a lack of clarity. Claims 8-9 recite the phrase a “color filter preferentially transmitting” which contains indefinite language of preference. Claim 13 recites: “said region” in singular form after having been introduced in plural form in claim 1 which creates a lack of clarity. Claim 14 recites “the same detection zone” and “the photodetection zone” which creates a lack of clarity between these claim terms. Claims 2-17 begin with “A device” in reference to claim 1 which creates a lack of clarity and should read “The device” for proper antecedent basis. Claims 1-20 recite the following limitations having antecedent basis issues: “Device for acquiring” in the first line of claim 1 should be properly introduced with an article; “the direction of said depth pixel” in claim 13 lacks antecedent basis; and “the same detection zone” and “the photodetection zone” in claim 16 each lack antecedent basis. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0305206 A1 to Deneuville (hereinafter “Deneuville”). Regarding claim 1, as best understood, Deneuville discloses a device for acquiring a 2D image and a depth image (claim 1), comprising: a first sensor formed in and on a first semiconductor substrate having a front face and a rear face (claim 1), the first sensor comprising a plurality of 2D image pixels, an interconnect stack located on the front face side of the first substrate and in which electrical connection tracks and/or terminals are formed (claim 2), and regions of a material distinct from that of the substrate located in the interconnect stack in line with 2D image pixels (material layer of interconnect stack 110 in line with pixels P1; Fig. 1; paragraphs [0031], [0035]); and adjoining the first sensor on the front face side of the first substrate, a second sensor formed in and on a second semiconductor substrate and comprising a plurality of depth pixels located opposite the regions of the first sensor (claim 1), wherein each region comprises a first portion extending into the interconnect stack from a first face of the interconnect stack facing the first substrate and a second portion extending from a second face of the interconnect stack facing the second substrate (material layer of interconnect stack 110 comprises first portion of amorphous silicon 50 region extending into first outer surface of stack 110 facing substrate 100 and second portion of amorphous silicon 50 region extending into second outer surface of stack facing second substrate 130; Fig. 1; paragraph [0038]), from a second face of the interconnect stack opposite the first substrate, to the first part , the first part having, in top view, a smaller surface area than the second part (first and second portions of region 50 may be defined such that the first has a smaller surface area than the second; Fig. 1), the material of the regions having, over a working wavelength range of the second sensor, an optical index greater than or equal to that of the material of the substrate (material layer of interconnect stack 110 comprises amorphous silicon 50 having a refractive index at 940 nm higher than that of single-crystal silicon substrate 100; Fig. 1; paragraphs [0031], [0038]). Regarding claim 2, as best understood, Deneuville discloses the device according to claim 1, wherein the material of the regions further has an absorption coefficient less than or equal to 10^-3 (material layer of interconnect stack 110 comprises amorphous silicon 50 which has an absorption coefficient in the range of between 10^2 and 10^4 cm^-1 at 940 nm; Fig. 1; paragraph [0038]). Regarding claim 3, as best understood, Deneuville discloses the device according to claim 1, wherein the material of the regions has an optical index greater than or equal to 3.5 (material layer of interconnect stack 110 comprises amorphous silicon 50 having a refractive index at 940 nm of about 3.6; paragraphs [0031], [0038]). Regarding claim 4, as best understood, Deneuville discloses the device according to claim 1, wherein the material of the regions is amorphous silicon (material layer of interconnect stack 110 comprises amorphous silicon 50; paragraphs [0031], [0038]). Regarding claim 5, as best understood, Deneuville discloses the device according to claim 1, wherein the electrical connection tracks and/or terminals penetrate inside the first part of each region (terminals 111 penetrate within material layer of interconnect stack 110; Fig. 1). Regarding claim 6, as best understood, Deneuville discloses the device according to claim 1, wherein each region is delimited laterally, over its entire periphery and height, by a dielectric material having a refractive index lower than that of the material of the region (stack 110 comprises dielectric material, e.g. silicon oxide, which has a refractive index lower than that of amorphous silicon 50; paragraphs [0035]-[0036]). Regarding claim 7, as best understood, Deneuville discloses the device according to claim 1, wherein the region extends over a thickness substantially equal to that of the interconnect stack and is flush with the face of the interconnect stack opposite the first semiconductor substrate (material layer of stack 110 having silicon 50 with equal thickness and flush with outer surfaces of stack 110 opposite substrate 100; Fig. 1). Regarding claim 8, as best understood, Deneuville discloses the device according to claim 1, wherein the first sensor is a color image sensor, each 2D image pixel comprising a color filter preferentially transmitting red, green or blue light (sensor C1 comprises color filter 118 transmitting red, green or blue light; paragraph [0043]). Regarding claim 9, as best understood, Deneuville discloses the device according to claim 8, wherein the regions are located solely in line with the 2D image pixels comprising the color filter preferentially transmitting blue light (material layer of interconnect stack 110 in line with pixels P1 having filter 118 transmitting blue light; Fig. 1; paragraphs [0031], [0035], [0043]). Regarding claim 10, as best understood, Deneuville discloses the device according to claim 8, wherein the regions are located in line with each 2D image pixel of the sensor (material layer of interconnect stack 110 in line with pixels P1; Fig. 1; paragraphs [0031], [0035]). Regarding claim 11, as best understood, Deneuville discloses the device according to claim 8, in which the pixels located in line with the regions are grouped in groups of four adjacent pixels (red, green, blue pixels P1 and pixel P2; Fig. 1; paragraphs [0043], [0046]). Regarding claim 12, as best understood, Deneuville discloses the device according to claim 11, wherein, for each group of four adjacent pixels, the region is common to all four pixels (material layer of interconnect stack 110 common to pixels P1, P2; Fig. 1; paragraphs [0043], [0046]). Regarding claim 13, as best understood, Deneuville discloses the device according to claim 1, further comprising, between each region of the first sensor and the corresponding depth pixel of the second sensor, alternating dielectric layers of distinct refractive indices, forming an anti-reflective stack for light rays passing through said region in the direction of said depth pixel (between material layer of interconnect stack 110 of the first sensor and the corresponding depth pixel of the second sensor, an alternation of dielectric layers having distinct refraction indices, forming an antireflection stack for light rays crossing said transmissive window towards said depth pixel; paragraph [0016]; claim 8). Regarding claim 14, as best understood, Deneuville discloses the device according to claim 1, in which the second sensor comprises, on the side facing the rear of the second semiconductor substrate, an interconnect stack in which electrical connection tracks and/or terminals are formed (claim 9). Regarding claim 15, as best understood, Deneuville discloses the device according to claim 1, in which each depth pixel of the second sensor comprises a SPAD-type photodiode (claim 10). Regarding claim 16, as best understood, Deneuville discloses the device according to claim 1, in which each depth pixel of the second sensor comprises several memory zones coupled to the same detection zone, and enables measurement of a phase shift between an amplitude-modulated light signal emitted by a light source of the device and a light signal received by the photodetection zone of the pixel, after reflection on a scene whose image is to be acquired (claim 11). Regarding claim 17, as best understood, Deneuville discloses the device according to claim 1, in which the first and second semiconductor substrates are made of monocrystalline silicon (single crystal substrates 100, 130; paragraphs [0031]-[0032]; claim 12). Regarding claim 18, as best understood, Deneuville discloses a method of manufacturing a device for acquiring a 2D image and a depth image (claim 1), the method comprising the following successive steps: a) forming, in and on a first semiconductor substrate, a first sensor having a front face and a rear face (claim 1), the first sensor comprising a plurality of 2D image pixels, an interconnect stack located on the front face side of the first substrate and in which electrical connection tracks and/or terminals are formed (claim 2), and regions of a material distinct from that of the substrate located in the interconnect stack in line with 2D image pixels (material layer of interconnect stack 110 in line with pixels P1; Fig. 1; paragraphs [0031], [0035]); and b) forming, in and on a second semiconductor substrate, a second sensor comprising a plurality of depth pixels located opposite the regions of the first sensor (claim 1); and c) joining the second sensor to the first sensor on the front face side of the first substrate (claim 1), wherein each region comprises a first portion extending into the interconnect stack from a first face of the interconnect stack facing the first substrate and a second portion extending (material layer of interconnect stack 110 comprises first portion of amorphous silicon 50 region extending into first outer surface of stack 110 facing substrate 100 and second portion of amorphous silicon 50 region extending into second outer surface of stack facing second substrate 130; Fig. 1; paragraph [0038]), from a second face of the interconnect stack opposite the first substrate, to the first part, the first part having, in top view, a smaller surface area than the second part (first and second portions of region 50 may be defined such that the first has a smaller surface area than the second; Fig. 1), the material of the regions having, over a working wavelength range of the second sensor, an optical index greater than or equal to that of the material of the substrate (material layer of interconnect stack 110 comprises amorphous silicon 50 having a refractive index at 940 nm higher than that of single-crystal silicon substrate 100; Fig. 1; paragraphs [0031], [0038]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Deneuville. Regarding claim 19, Deneuville discloses the method according to claim 18, comprising the following steps: forming a first part of the interconnect stack; forming the first part of the region; forming a second portion of the interconnect stack; and forming the second part of the region (Figs. 2A-2J; paragraph [0063]). Deneuville fails to disclose comprising the following successive steps: forming a first part of the interconnect stack; forming the first part of the region; forming a second portion of the interconnect stack; and forming the second part of the region. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified the steps already disclosed by Deneuville to be in a particular successive order in order to potentially provide reduced manufacturing cost and process simplification. Regarding claim 20, Deneuville discloses the method according to claim 19, in which the first and second parts of the region are formed after the interconnect stack has been completed (first and second portions of amorphous silicon 50 are formed after remainder of material layer of interconnect stack 110 is formed; Figs. 2A-2J; paragraph [0063]). Conclusion The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: each of US 2020/0279881 A1 to Jin et al., US 2015/0049229 A1 to Liu et al., and US 2021/0152766 A1 to Byun disclose image sensing devices having related structural and orientational relationships. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IAN DEGRASSE/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Oct 11, 2023
Application Filed
Apr 04, 2026
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604536
Semiconductor Device and Method For Manufacturing Semiconductor Device
2y 5m to grant Granted Apr 14, 2026
Patent 12593473
THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY PANEL
2y 5m to grant Granted Mar 31, 2026
Patent 12563771
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Feb 24, 2026
Patent 12550347
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CIRCUIT
2y 5m to grant Granted Feb 10, 2026
Patent 12520522
SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR
2y 5m to grant Granted Jan 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
61%
With Interview (-22.2%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 12 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month