DETAILED ACTION
This Office action is in response to the application filed on 11 October 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 3 at line 1, “the Zener diode” lacks antecedent basis in the claim. Further, it is not clear whether the correct scope of claim 3 would be to interpret this as “a Zener diode”, or instead that claim 3 should be dependent on claim 2, which properly introduces the term, instead of claim 1 as filed.
For examination purposes, claim 3 is being interpreted as dependent on claim 2.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 11-12 and 18-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ghosh et al. (US 2023/0161364; “Ghosh”).
In re claims 1 and 11, Ghosh discloses a high voltage regulation circuit (Fig. 11), comprising:
a monolithic semiconductor substrate having a surface covered with a gallium nitride layer (substrate and GaN layer are not explicitly shown; however the presence of the substrate is taught in Ghosh: see e.g., Abstract, [0021] [0059]; and the presence of a GaN layer is evident from the GaN HEMTs fabricated on the substrate: id.);
a voltage regulator circuit (actual circuitry shown in Fig. 111) that includes:
a first terminal (VIN);
a second terminal (the node at top end of C1);
a third terminal (VOUT);
a first resistor (R3) between the first terminal and the second terminal2;
a first d-mode type HEMT transistor (Q2: see annotation of Fig. 11, below) between the first terminal and the second terminal; and
a second d-mode type HEMT transistor (also Q2: see annotations below) between the first terminal and the third terminal;
wherein a midpoint between the first resistor and the first transistor (the node corresponding to the claimed second terminal (see annotation below) is interpreted to correspond to the midpoint between first resistor R3 and first transistor Q2) is coupled to gates of the first and second transistors (see Fig. 11: said midpoint is directly connected to gates of both the first and second transistors).
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In re claim 2, Ghosh discloses that the circuit (Fig. 11) further comprises, between the second terminal (see annotation above) and a reference terminal (ground), a zener diode (Fig. 11: “VOLTAGE REFERENCE” Zener diode).
In re claim 4, Ghosh discloses wherein the second terminal or the third terminal are adapted to delivering a power supply voltage (noting that the term “adapted” is interpreted as only requiring a capability to perform the claimed function, both the first terminal VIN and second terminal VOUT in Fig. 11 of Ghosh are clearly adapted in this manner in that they both actually deliver a respective power supply voltage).
In re claims 5 and 12, Ghosh discloses that the circuit further comprises, between the first resistor and the first transistor, a third d-mode type HEMT transistor (Q4, see annotation of Fig. 11 on previous page) having its gate coupled to a middle node between the first resistor and the third transistor (Fig. 11: the middle node is interpreted to be the node that is between the bottom end of R3 and the gate of Q4).
In re claim 18, Ghosh discloses a device (Fig. 11), comprising:
a substrate (substrate and GaN layer are not explicitly shown; however the presence of the substrate is taught in Ghosh: see e.g., Abstract, [0021] [0059]);
a gallium nitride layer on the substrate (the presence of a GaN layer is evident from the GaN HEMTs fabricated on the substrate: id.);
a voltage regulator circuit (circuitry of Fig. 11; see the Examiner’s annotations of such, provided above in this Office action) that includes:
a first terminal (VIN);
a second terminal (see annotation of second terminal in Fig. 11, above);
a third terminal (VOUT);
a first d-mode type HEMT transistor (Q2 as annotated in Fig. 11, above) between the first terminal and the second terminal, a first gate of the first transistor is coupled to a source/drain of the first transistor (gate of 1st transistor Q2 is coupled to gate of 1st transistor Q2 through R2); and
a second d-mode type HEMT transistor (Q2 as annotated in Fig. 11 above) between the first terminal and the third terminal, a second gate of the second transistor being coupled to the first gate of the first transistor (gates of 1st transistor Q2 and 2nd transistor Q2 are coupled together as shown in Fig. 11).
In re claim 19, Ghosh discloses a first resistor (R3 as annotated in Fig. 11, above) between the first terminal and the second terminal (Fig. 11);
a first capacitor (C1) coupled between the third terminal and ground (Fig. 11: C1 coupled between third terminal, via R2 and 2nd transistor Q2, and ground).
In re claim 20, Ghosh discloses a third transistor (Fig. 11: Q4 as annotated above) coupled between the first resistor and the first transistor (see Fig. 11); and
a fourth transistor (Fig. 11: Q5) coupled between the first terminal and a third gate of the third transistor (Fig. 11: Q5 is coupled between 1st terminal VIN, via resistor R2, and gate of 3rd transistor Q4).
Allowable Subject Matter
Claims 6-10 and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 would be allowable if rewritten according to the Examiner’s suggestion to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, under the interpretation that it depends from claim 2 as explained in the rejection, above, under 35 USC 112(b), the closest prior art in Ghosh discloses the voltage regulation circuit including all elements of both claims 1 and 2 (see rejections above). However, Ghosh does not further disclose that the zener diode is formed on a portion of the semiconductor substrate which is not covered with the gallium nitride layer, as recited in claim 3. Furthermore, the additional prior art on record does not supply a teaching or suggestion that it would have been obvious to modify the voltage regulator in Ghosh in this manner.
With respect to claims 6-10, the closest prior art in Ghosh discloses the voltage regulation circuit including all elements of both claims 1 and 5 (see rejections above). However, Ghosh does not further disclose a fifth d-mode type HEMT transistor that is between the first terminal and a first node adapted to delivering a power supply voltage, and the fifth transistor also having a gate coupled to the gate of the third transistor, as required by the language of claim 6. Furthermore, the additional prior art on record does not supply a teaching or suggestion that it would have been obvious to modify the voltage regulator in Ghosh in this manner.
With respect to claims 13-17, the closest prior art in Ghosh discloses the voltage regulation circuit including all elements of both claims 11 and 12 (see rejections above). However, Ghosh does not further disclose a fifth d-mode type HEMT transistor that is between the first terminal and a first node adapted to delivering a power supply voltage and the fifth transistor having a gate coupled to the gate of the third transistor, as is required by the language of claim 13. Furthermore, the additional prior art on record does not supply a teaching or suggestion that it would have been obvious to modify the voltage regulator in Ghosh in this manner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2020/0357907 discloses a III-V semiconductor device with integrated protection functions, including a silicon substrate having a gallium nitride layer formed above it.
US 2023/0178543 discloses a semiconductor device including a first resistor and first, second, and third transistors (Fig. 1).
US 2023/0188128 discloses a voltage regulator circuit and UVLO circuit fabricated on a gallium nitride layer disposed on a substrate.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 Fig. 11 of Ghosh is reproduced, below, with annotations by the examiner for clarity
2 It is noted that the claim term “between” is interpreted broadly and allows for indirect connections and intervening elements.