DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-12, 14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan et al, US Patent 10,181,421 in view of Lin et al, US Patent 10,026,687 (both newly submitted)
Regarding claim 1, Ryan teaches a semiconductor structure comprising:
a plurality of lower metal lines 225/240 in a first metal level 205/210;
a transition via 255/260 directly on top of the plurality of lower metal lines; and
wherein at least a first lower metal line of the plurality of lower metal lines has a recessed region 240 and a rest region 225, the recessed region is directly underneath the transition via and filled with a dielectric material (column 4, line 55); and isolates the rest region of the first lower metal line from the transition via (figure 2H).
Ryan fails to teach an upper metal line directly on top of the transition via, the upper metal line being in a second metal level and orthogonal to the plurality of lower metal lines
However, Lin teaches an upper metal line 38 directly on top of the transition via 20, the upper metal line being in a second metal level and orthogonal to the plurality of lower metal lines 14 (Note, 38 runs from top to bottom of figure 2, while 14 runs left to right of figure 3) in teaching that there are multiple wiring layers used in a semiconductor component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lim with that of Ryan because it is generally-known in the art that semiconductor component may contain multiple wiring layer to improved resistance characteristics, minimizes capacitance for a lower wiring structure, e.g., at M0 layer, as well as provides area efficiencies in the chip manufacturing process.
Regarding claim 2, Ryan teaches the transition via is electrically insulated from the rest region of the first lower metal line and conductively connected to at least a second lower metal line of the plurality of lower metal lines (figure 2H).
Regarding claims 3 and 4, Ryan and Lin fail to teach upper metal line has a width that is about 9 times as wide as a width of the first lower metal line and the plurality of lower metal lines have a width of about 40nm and a pitch of about 80nm and the upper metal line has a width of about 360nm, and wherein the transition via has a width of about 324nm and a length of about 324nm; and is directly above at least 4 of the plurality of lower metal lines.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 5, Ryan and Lin fails to teach the recessed region of the first lower metal line has a length that is equal to or larger than a length of the transition via
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 7, Ryan teaches the transition via and the first lower metal line, including the recessed region thereof, form a low pass decoupling capacitor (figure 2H).
Regarding claim 8, Ryan teaches a semiconductor structure comprising:
a plurality of lower metal lines 225/240 in a first metal level 205/210;
a transition via 255/260 directly on top of the plurality of lower metal lines; and
wherein at least a first and a second lower metal line of the plurality of lower metal lines each has a recessed region 240 and a rest region 225, the recessed region is directly underneath the transition via and isolates the rest region of the first and the second lower metal line from the transition via (figure 2H).
Ryan fails to teach an upper metal line on top of the transition via, the upper metal line being one of a plurality of upper metal lines in a second metal level.
However, Lin teaches an upper metal line 38 on top of the transition via 20, the upper metal line being one of a plurality of upper metal lines in a second metal level (figure 3) in teaching that there are multiple wiring layers used in a semiconductor component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lim with that of Ryan because it is generally-known in the art that semiconductor component may contain multiple wiring layer to improved resistance characteristics, minimizes capacitance for a lower wiring structure, e.g., at M0 layer, as well as provides area efficiencies in the chip manufacturing process.
Regarding claim 9, Ryan teaches the transition via is conductively connected to at least a third lower metal line of the plurality of lower metal lines (figure 2H).
Regarding claims 10-12, Ryan and Lin fail to teach to teach the upper metal line has a width that is about 9 times as wide as a width of the first lower metal line and the plurality of upper metal lines have a width of about 360nm and a pitch of about 720nm and the plurality of lower metal lines have a width of about 40nm and a pitch of about 80nm, and wherein the transition via has a width of about 324nm and a length of about 324nm; and is directly above at least 4 of the plurality of lower metal lines, wherein the recessed region of the first lower metal line has a length of about 360nm.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 14, Ryan teaches a method of forming a semiconductor structure comprising:
forming a plurality of lower metal lines 225 of a first metal level in a substrate (figure 2A);
recessing a portion of a first lower metal line of the plurality of lower metal lines to create a recessed region and a rest region of the first lower metal line (figure 2B);
filling the recessed region of the first lower metal line with a dielectric material 235/240 (figures 2C-2D);
forming a first dielectric layer 245 on top of the first metal level and creating an opening 250/230 in the first dielectric layer to expose the recessed region of the first lower metal line and expose a second lower metal line of the plurality of lower metal lines (figure 2F-2G);
filling the opening in the first dielectric layer with a conductive material to form a transition via 260 (figure 2H).
Ryan fails to teach forming a second dielectric layer on top of the first dielectric layer and on top of the transition via.
However, Lin teaches forming a second dielectric layer 26 on top of the first dielectric layer 18/24 and on top of the transition via 20 (figure 3) in teaching that there are multiple wiring layers used in a semiconductor component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lim with that of Ryan because it is generally-known in the art that semiconductor component may contain multiple wiring layer to improved resistance characteristics, minimizes capacitance for a lower wiring structure, e.g., at M0 layer, as well as provides area efficiencies in the chip manufacturing process.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lim with that of Ryan because it is generally-known in the art that semiconductor component may contain multiple wiring layer to improved resistance characteristics, minimizes capacitance for a lower wiring structure, e.g., at M0 layer, as well as provides area efficiencies in the chip manufacturing process.
Regarding claim 16, Ryan teaches the transition via is isolated from the rest region of the first lower metal line by the recessed region and is conductively connected to the second lower metal line (figure 2H).
Regarding claim 17-18, Ryan and Lin fail to teach the one or more upper metal lines have a width of about 360nm and a pitch of about 720nm, and the plurality of lower metal lines have a width of about 40nm and a pitch of about 80nm, creating the opening in the first dielectric layer comprises create the opening to expose at least 4 of the plurality of lower metal lines.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 19, Ryan teaches recessing the portion of the first lower metal line comprises selectively etching the portion of the first lower metal line to create a recess such that the recess has a height that is equal to or less than half of a height of the first lower metal line (figure 3).
Regarding claim 20, while Ryan teaches recessing the portion of the first lower metal line comprises selectively etching the portion of the first lower metal line to create a recess (figure 2D), Ryan and Lin fail to teach the recess has a length that is equal to or longer than a length of the transition via.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryan and Lin as applied to claims above, and further in view of Pethe et al, US Patent 9,461,143 (as cited in previous Office Action).
Regarding claim 6, Ryan and Lin fail to teach the dielectric material in the recessed region of the first lower metal line is a high-k dielectric having a dielectric constant equal to or larger than 4.
However, Pethe teaches the dielectric material in the recessed region of the first lower metal line is a high-k dielectric having a dielectric constant equal to or larger than 4 (column 10, lines 16-22) as one of several conventional dielectrics that is generally-used in the art to form a cap layer on a lower metallic film
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Pethe with that of Ryan and Lin because hafnium oxide is one of several conventional dielectrics that is generally-used in the art to form a cap layer on a lower metallic film.
Regarding claim 13, while Ryan teaches the transition via and the first lower metal line, including the recessed region, form a low pass decoupling capacitor (figure 2H), Ryan and Lin fail to teach the dielectric material in the recessed region of the first lower metal line is hafnium-oxide (HfO) having a dielectric constant larger than 4.
Pethe teaches the dielectric material in the recessed region of the first lower metal line is hafnium-oxide (HfO) having a dielectric constant larger than 4 (column 10, lines 16-22) as one of several conventional dielectrics that is generally-used in the art to form a cap layer on a lower metallic film
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Pethe with that of Ryan and Lin because hafnium oxide is one of several conventional dielectrics that is generally-used in the art to form a cap layer on a lower metallic film.
Response to Arguments
Applicant’s arguments, see page 6, filed 4 February 2026, with respect to the rejection(s) of claim(s) 1, 9, and 14 under the reference of Tanwar have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly cited prior art
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2020/0098688, issued to Shi et al, discloses a self-aligned chamferless interconnect structure.
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