Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed July 23, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 14, 18
b. Pending: 1-20
Claims 1, 14, and 18 have been amended.
Claim Rejections - 35 USC § 112
The 112(b) claim rejections are withdrawn pursuant to claim amendments.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Kim et al. (US Pub. 20110222339 A1; “Kim”) and Yoo (US Pub. 20160099060 A1). Kim paras. [0037], [0067], and [0072] and Figs. 1-6 are relevant to claims 1, 14, and 18; and Yoo paras. [0066]-[0067], [0092]-[0095], and [0122] and Figs. 4 and 7-8 are relevant to claims 1, 14, and 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20110222339 A1) in view of Yoo (US Pub. 20160099060 A1).
Regarding independent claim 1, Kim discloses a memory device (Fig. 1: flash memory device 100; [0027]) comprising:
a memory cell (Fig. 2: memory cell MCn; [0038]) that is configured to have data stored therein ([0032] describes data storage in memory cell array 110); and
a control logic (Fig. 1: control logic circuit 160; [0027]) that is configured to determine a dummy voltage from at least a first dummy voltage and a second dummy voltage based on a location of a selected word line electrically connected to the memory cell, and is configured to apply the dummy voltage to dummy word lines ([0067]: the voltage applied to the dummy word line may be controlled based on the distance between a selected word line and the dummy word line. Examiner acknowledges that Kim only teaches a single dummy word line, however it is known in the art that multiple dummy word lines, one or more on each end of NAND strings in an array, are often included to reduce disturbances. Furthermore, Kim is concerned with reducing interference and charge loss, see title and Abstract, so adding additional dummy word lines would make sense), wherein the first dummy voltage is applied to the first dummy word line when a location of the selected word line is a first location, and the second dummy voltage different from the first dummy voltage is applied to the first dummy word line when a location of the selected word line is a second location different from the first location ([0067]: when a first word line closer to dummy word line than a second word line is selected, a first voltage may be applied to the dummy word line that is lower than a second voltage applied to the dummy word line when the second word line is selected. For example, when a word line n rows away from a dummy word line is selected (when n=1, this means the immediately adjacent row), the voltage applied to the dummy word line may be lower than when a word line n+1 rows away from a dummy word line is selected), and
Kim does not disclose:
dummy word lines including a first dummy word line and a second dummy word line
wherein the first dummy word line and the second dummy word line are adjacent to opposing ends in a vertical direction of a memory NAND string including the memory cell, respectively.
However, Yoo teaches:
dummy word lines including a first dummy word line and a second dummy word line (Fig. 4: dummy word lines SWL1, SWL2, DWL1, and DWL2; [0069] & [0071])
wherein the first dummy word line and the second dummy word line are adjacent to opposing ends in a vertical direction of a memory NAND string ([0006]: NAND type) including the memory cell, respectively ([0067]: Each of the plurality of cell strings CS11′ to CS1m′, CS21′ to CS2m′ may include…at least one of source side dummy memory cells SMC1 and SMC2…may include at least one of drain side dummy memory cells DMC1 to DMC2; also see Fig. 4).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Yoo to Kim wherein there are dummy word lines including a first dummy word line and a second dummy word line, and wherein the first dummy word line and the second dummy word line are adjacent to opposing ends in a vertical direction of a memory NAND string including the memory cell, respectively in order to improve the reliability of a program operation by controlling the voltages on multiple dummy word lines (Yoo, [0110]).
Regarding independent claim 14, Kim discloses a memory device (Fig. 1: flash memory device 100; [0027]) comprising:
a memory cell (Fig. 2: MCn) that is configured to have data stored therein ([0032]); and
a control logic (Fig. 1: 160) that is configured to:
apply a dummy voltage from at least a first dummy voltage and a second dummy voltage based on a location of the selected word line to dummy word lines ([0067]: the voltage applied to the dummy word line may be controlled based on the distance between a selected word line and the dummy word line. Examiner acknowledges that Kim only teaches a single dummy word line, however it is known in the art that multiple dummy word lines, one or more on each end of NAND strings in an array, are often included to reduce disturbances. Furthermore, Kim is concerned with reducing interference and charge loss, see title and Abstract, so adding additional dummy word lines would make sense), wherein the first dummy voltage is applied to the first dummy word line and the second dummy word line when a location of the selected word line is a first location, and the second dummy voltage different from the first dummy voltage is applied to the first dummy word line and the second dummy word line when a location of the selected word line is a second location different from the first location ([0067]: when a first word line closer to dummy word line than a second word line is selected, a first voltage may be applied to the dummy word line that is lower than a second voltage applied to the dummy word line when the second word line is selected. For example, when a word line n rows away from a dummy word line is selected (when n=1, this means the immediately adjacent row), the voltage applied to the dummy word line may be lower than when a word line n+1 rows away from a dummy word line is selected), and
Kim does not disclose:
apply a verification voltage to a selected word line electrically connected to the memory cell during a verifying period for verifying the memory cell;
including a first dummy word line and a second dummy word line during the verifying period
the first dummy word line and the second dummy word line are adjacent to opposing ends in a vertical direction of a memory NAND string including the memory cell, respectively; and
apply a verification pass voltage to unselected word lines other than the dummy word lines during the verifying period.
However, Yoo teaches:
apply a verification voltage to a selected word line electrically connected to the memory cell during a verifying period for verifying the memory cell ([0122]: At a fourth time T4, a verification voltage Vvrf may be applied to the selected normal word line WLsel…By the verification voltage Vvrf, a threshold voltage of the selected normal memory cell may be read by a read/write circuit 140 (referring to FIG. 1) through a corresponding bit line);
including a first dummy word line and a second dummy word line (Fig. 4: dummy word lines SWL1, SWL2, DWL1, and DWL2; [0069] & [0071]) during the verifying period ([0122]: At a fourth time T4…A read-pass voltage Vrd may be applied to the non-selected normal word lines WLusel, the first and second drain side dummy word lines DWL1 and DWL2, and the first and second source side dummy word lines SWL1 and SWL2. Examiner notes that “including a first dummy word line and a second dummy word line” refers to a control logic applying dummy voltages to dummy word lines. Therefore, also see [0045]: The control logic 160 may be configured to control overall operations of the semiconductor memory device 100 in response to the control signal CTRL)
the first dummy word line and the second dummy word line are adjacent to opposing ends in a vertical direction of a memory NAND string ([0006]: NAND type) including the memory cell, respectively ([0067]: Each of the plurality of cell strings CS11′ to CS1m′, CS21′ to CS2m′ may include…at least one of source side dummy memory cells SMC1 and SMC2…may include at least one of drain side dummy memory cells DMC1 to DMC2; also see Fig. 4); and
apply a verification pass voltage to unselected word lines other than the dummy word lines during the verifying period ([0122]: At a fourth time T4…A read-pass voltage Vrd may be applied to the non-selected normal word lines WLusel).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Yoo to Kim wherein the control logic is configured to apply a verification voltage to a selected word line electrically connected to the memory cell during a verifying period for verifying the memory cell; including a first dummy word line and a second dummy word line during the verifying period, the first dummy word line and the second dummy word line are adjacent to opposing ends in a vertical direction of a memory NAND string including the memory cell, respectively; and apply a verification pass voltage to unselected word lines other than the dummy word lines during the verifying period in order to improve the reliability of a program operation by controlling the voltages on multiple dummy word lines (Yoo, [0110]).
Regarding independent claim 18, Kim discloses a memory device operating method ([0008]: a method of operating a nonvolatile memory device is disclosed) comprising:
determining a dummy voltage from at least a first dummy voltage and a second dummy voltage based on a location of the selected word line ([0067]: the voltage applied to the dummy word line may be controlled based on the distance between a selected word line and the dummy word line), the first dummy voltage corresponding to a first location of the selected word line, the second dummy voltage corresponding to a second location of the selected word line, the second location different from the first location ([0067]: when a first word line closer to dummy word line than a second word line is selected, a first voltage may be applied to the dummy word line that is lower than a second voltage applied to the dummy word line when the second word line is selected. For example, when a word line n rows away from a dummy word line is selected (when n=1, this means the immediately adjacent row), the voltage applied to the dummy word line may be lower than when a word line n+1 rows away from a dummy word line is selected); and
applying the first dummy voltage to dummy word lines ([0067]; Examiner acknowledges that Kim only teaches a single dummy word line, however it is known in the art that multiple dummy word lines, one or more on each end of NAND strings in an array, are often included to reduce disturbances. Furthermore, Kim is concerned with reducing interference and charge loss, see title and Abstract, so adding additional dummy word lines would make sense), when a location of the selected word line is the first location, and applying the second dummy voltage to the dummy word lines respectively when the location of the selected word line is the second location ([0067]).
Kim does not disclose:
applying a verification voltage to a selected word line electrically connected to a memory cell having data stored therein;
dummy word lines located at an upper end and a lower end of a memory NAND string including the memory cell, respectively
However, Yoo teaches:
applying a verification voltage to a selected word line electrically connected to a memory cell ([0122]: At a fourth time T4, a verification voltage Vvrf may be applied to the selected normal word line WLsel…By the verification voltage Vvrf, a threshold voltage of the selected normal memory cell may be read by a read/write circuit 140 (referring to FIG. 1) through a corresponding bit line) having data stored therein ([0007]: The memory cell array may include normal memory cells for storing data);
dummy word lines located at an upper end and a lower end of a memory NAND string ([0006]: NAND type) including the memory cell, respectively ([0067]: Each of the plurality of cell strings CS11′ to CS1m′, CS21′ to CS2m′ may include…at least one of source side dummy memory cells SMC1 and SMC2…may include at least one of drain side dummy memory cells DMC1 to DMC2; also see Fig. 4),
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Yoo to Kim wherein the operating method comprises applying a verification voltage to a selected word line electrically connected to a memory cell having data stored therein; and there are dummy word lines located at an upper end and a lower end of a memory NAND string including the memory cell in order to improve the reliability of a program operation by controlling the voltages on multiple dummy word lines (Yoo, [0110]).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20110222339 A1) and Yoo (US Pub. 20160099060 A1) as applied to claim 1 above, and further in view of Fastow (US Pub. 20190043591 A1).
Regarding claim 2, Kim and Yoo together disclose the limitations of claim 1. Further, through Yoo:
wherein the memory NAND string is on a substrate ([0033]: Each of the plurality of memory blocks may include a plurality of memory cells stacked above a substrate) and
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Yoo to modified Kim wherein the memory NAND string is on a substrate in order to improve the reliability of a program operation by controlling the voltages on multiple dummy word lines (Yoo, [0110]).
Neither Kim nor Yoo discloses:
comprises a multi-stack structure that includes a first stack and a second stack on the first stack,
wherein the first stack is between the second stack and the substrate, and
wherein third and fourth ones of the dummy word lines are adjacent to a junction between the first stack and the second stack.
However, Fastow teaches:
comprises a multi-stack structure (Fig. 3: floating gate NAND memory array architecture 300; [0046]) that includes a first stack (bottom deck 360; [0046]) and a second stack (top deck 310; [0046]) on the first stack,
wherein the first stack is between the second stack and the substrate (per Fig. 3, the bottom deck 360 is between the top deck 310 and the source connection 303; [0046]; [0038]: memory cells 103 may be stacked over some other memory cells 103 in multiple levels over a substrate (e.g., a semiconductor substrate) of memory device 100, forming pillars), and
wherein third and fourth ones of the dummy word lines are adjacent to a junction between the first stack and the second stack (per Fig. 3, one of the two interface dummy WLs 317 and one of the two interface dummy WLs 351 are adjacent to poly plug 350; [0047]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fastow to modified Kim wherein there is a multi-stack structure that includes a first stack and a second stack on the first stack, wherein the first stack is between the second stack and the substrate, and wherein third and fourth ones of the dummy word lines are adjacent to a junction between the first stack and the second stack in order to reduce block size and operate each deck independently without creating disturbances (Fastow, [0024]).
Regarding claim 3, Kim, Yoo, and Fastow together disclose the limitations of claim 2, and further through Kim:
wherein the control logic (Fig. 1: 160) is configured to determine the dummy voltage based on the location of the selected word line ([0067])
Also, Fastow teaches:
determine the dummy voltage based on the location of the selected word line in one of the first or second stacks (in reference to Fig. 4, per [0056]: As regards interfacial dummy WLs 451, belonging to the selected bottom deck, they may be biased so as to form a graded transition region between the active WLs of the selected and unselected decks. Thus, in this example, their voltage bias may be, for example, between 0V (that of the active WLs of the bottom deck) and 2.0V, as shown, which transitions up to the 5-7V to float that the upper active WLs are biased at. Moreover, in embodiments, the edge dummy WLs of the selected deck may be biased so as to form a graded transition between the select gate and the active WLs).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fastow to modified Kim wherein the dummy voltage is determined based on the location of the selected word line in one of the first or second stacks in order to reduce block size and operate each deck independently without creating disturbances (Fastow, [0024]).
Regarding claim 4, Kim, Yoo, and Fastow together disclose the limitations of claim 2. Kim discloses that the control logic determines dummy voltages based on the location of the selected word line.
Also, Fastow teaches:
determine the dummy voltage based on the location of the selected word line in one of the first or second stacks (per Fig. 4 and [0056], depending on the location of the selected word line in either the bottom deck or top deck, the dummy voltage would either be 0-2V or would be floating at 5-7V).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fastow to modified Kim wherein the dummy voltage is determined based on the location of the selected word line in one of the first or second stacks in order to reduce block size and operate each deck independently without creating disturbances (Fastow, [0024]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20110222339 A1), Yoo (US Pub. 20160099060 A1), and Fastow (US Pub. 20190043591 A1) as applied to claim 4 above, and further in view of Joo et al. (US Pub. 20120307561 A1; “Joo”).
Regarding claim 5, Kim, Yoo, and Fastow together disclose the limitations of claim 4. Kim discloses that the control logic determines dummy voltages based on the location of the selected word line.
Also, Fastow discloses:
wherein, in a case of Top-to-Bottom (T2B) programming (in reference to Fig. 6, per [0063]: In embodiments with two decks, the programming sequence may, for example, progress from poly plug 659 outward towards drain 601, in the case of the top deck program 640, or downwards towards source 660, as in the case of bottom deck program 630. Examiner concludes that bottom deck programming is analogous to T2B programming),
Neither Kim, Yoo, nor Fastow discloses:
the control logic is configured to apply the dummy voltage having a first voltage when the selected word line is located in the first stack, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the selected word line is located in the second stack.
However, Joo teaches:
the control logic is configured to apply the dummy voltage (per [0062], the access circuit 22 applies dummy word line signals to the dummy word lines; [0067]: The control logic 50 controls the overall operation of the access circuit 22) having a first voltage when the selected word line is located in the first stack (per Fig. 15 and [0110], WL7 is selected, which per Fig. 14 is in the first, or lower, stack; also per Fig. 15, intermediate dummy word line DWL1 has the second dummy word line voltage VDUM2, which is higher than the first dummy word line voltage VDUM1), and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the selected word line is located in the second stack (per Fig. 16, WL12 is selected, which per Fig. 14 is in the second, or upper, stack; also per Fig. 16, intermediate dummy word line DWL1 has the first dummy word line voltage VDUM1, which is lower than the second dummy word line voltage VDUM2).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Joo to modified Kim wherein the control logic is configured to apply the dummy voltage having a first voltage when the selected word line is located in the first stack, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the selected word line is located in the second stack in order to prevent a decrease in read margin due to disturbance and improve the operating characteristics of the non-volatile memory device (Joo, [0006]).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20110222339 A1) and Yoo (US Pub. 20160099060 A1) as applied to claim 1 above, and further in view of Shim et al. (US Pub. 20170062065 A1; “Shim”).
Regarding claim 11, Kim and Yoo together disclose the limitations of claim 1. Kim discloses control logic and a memory cell. Neither Kim nor Yoo discloses:
wherein the control logic is configured to determine the dummy voltage based on a program/erase cycle (P/E cycle) or a temperature of the memory cell.
However, Shim teaches:
wherein the control logic is configured to determine the dummy voltage based on a program/erase cycle (P/E cycle) or a temperature of the memory cell ([0026]: the dummy pulse controller may cause the voltage generator to apply the dummy pulse to at least some of the memory blocks based on at least one of a number of a program/erase cycle of the first memory block, an elapsed time from a completion of the program loop and an operating temperature of the nonvolatile memory device).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Shim to modified Kim wherein the control logic is configured to determine the dummy voltage based on a program/erase cycle (P/E cycle) or a temperature of the memory cell in order to reduce the number of error bits in a read operation by applying a dummy pulse to memory blocks before the read operation (Shim, [0030] & [0203]).
Regarding claim 12, Kim, Yoo, and Shim together disclose the limitations of claim 11. Kim discloses control logic and a memory cell.
Further, through Shim:
wherein the control logic is configured to apply the dummy voltage ([0026]) having a first voltage when the P/E cycle of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the P/E cycle of the memory cell is lower than the first reference value ([0149]: The dummy pulse control signal generator 600 may apply the dummy pulse control signal DPC to one of the high voltage generator 710 and the low voltage generator 730 based on at least one of the first counting value CV1, the second counting value CV; [0132]: The program/erase cycle counter 540 counts a number of program/erase cycle on the selected memory cells based on the decoded command D_CMD and the row address R_ADDR and provides the dummy pulse controller 600 with a first counting value CV1. The first counting value CV1 indicates the counted number of the program/erase cycle on the selected memory cells; [0150]: The high voltage generator 710 may periodically apply the read pass voltage VRPASS as the dummy pulse DP to at least some of the memory blocks BLK1˜BLKz in response to the dummy pulse control signal DPC. The low voltage generator 730 may periodically apply the read voltage VRD as the dummy pulse DP to at least some of the memory blocks BLK1˜BLKz in response to the dummy pulse control signal DPC. Examiner concludes that CV1 is a first reference value and that when CV1 is higher than a number, the dummy voltages may be high and vice versa).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Shim to modified Kim wherein the control logic is configured to apply the dummy voltage having a first voltage when the P/E cycle of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the P/E cycle of the memory cell is lower than the first reference value in order to reduce the number of error bits in a read operation by applying a dummy pulse to memory blocks before the read operation (Shim, [0030] & [0203]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20110222339 A1), Yoo (US Pub. 20160099060 A1), and Shim (US Pub. 20240220142 A1) as applied to claim 11 above, and further in view of Nam (KR 20180021964 A).
Regarding claim 13, Kim, Yoo, and Shim together disclose the limitations of claim 11. Kim discloses control logic, a dummy voltage, and a memory cell.
Neither Kim, Yoo, nor Shim discloses:
wherein the control logic is configured to apply the dummy voltage having a first voltage when the temperature of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage higher than the first voltage when the temperature of the memory cell is lower than the first reference value.
However, Nam teaches:
wherein the control logic (Fig. 1: dummy word line pre-pulse controller (DWLPC) within control logic circuit 119) is configured to apply the dummy voltage ([0068]: a pre-pulse (VDP) applied to dummy memory cells) having a first voltage (first voltage in screenshot of Fig. 13 below) when the temperature of the memory cell is higher than a first reference value (first reference value in screenshot below), and is configured to apply the dummy voltage (VDP) having a second voltage (second voltage in screenshot below) higher than the first voltage when the temperature of the memory cell is lower than the first reference value.
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436
650
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It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Nam to modified Kim wherein the control logic is configured to apply the dummy voltage having a first voltage when the temperature of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage higher than the first voltage when the temperature of the memory cell is lower than the first reference value in order to reduce the amount of stress applied to the memory cells of the unselected cell strings and improving the reliability of data written to the memory cells (Nam, [0048]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20110222339 A1) and Yoo (US Pub. 20160099060 A1) as applied to claim 14 above, and further in view of Hwang (US Pub. 20220328101 A1).
Regarding claim 15, Kim and Yoo together disclose the limitations of claim 14. Kim discloses control logic and a dummy voltage.
Neither Kim nor Yoo disclose:
apply the dummy voltage in a word line setup section of the verifying period.
However, Hwang teaches:
apply the dummy voltage in a word line setup section of the verifying period (per Fig. 8, a voltage is applied to dummy word line CPWL during the Verify Phase, and during this time, voltages are applied to the word lines WLs; [0113]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hwang to modified Kim wherein the dummy voltage is applied in a word line setup section of the verifying period in order to improve the reliability of operations on a memory block (Hwang, [0093]).
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Pub. 20110222339 A1) and Yoo (US Pub. 20160099060 A1) as applied to claims 14 and 18 above, respectively, and further in view of Ray (US Pat. 9704588 B1).
Regarding claim 16, Kim and Yoo together disclose the limitations of claim 14. Kim discloses control logic and a dummy voltage. Neither Kim nor Yoo disclose:
apply the dummy voltage in a bit line setup section of the verifying period.
However, Ray teaches:
apply the dummy voltage in a bit line setup section of the verifying period (per Fig. 10, a voltage Vread is applied to the Dummy WL while the selected BL is being charged; col. 19, lines 35-36: FIG. 10 is a timing diagram describing waveforms during a read or verify operation according to one embodiment).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ray to modified Kim wherein the dummy voltage is applied in a bit line setup section of the verifying period in order to improve performance and decrease power consumption by eliminating a preconditioning current (Ray, col. 25, lines 60-63).
Regarding claim 20, Kim and Yoo together disclose the limitations of claim 18. Kim discloses applying a dummy voltage. Neither Kim nor Yoo disclose:
applying the dummy voltage in a word line setup section or a bit line setup section following the word line setup section.
However, Ray teaches:
applying the dummy voltage in a word line setup section (per Fig. 10, Vread is applied to the Dummy WL while Selected WL is charged to Vread) or a bit line setup section following the word line setup section (see rejection of claim 16 above; the peak voltage, Vpre, on the Selected BL occurs after the selected WL is charged with Vread).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ray to modified Kim wherein the dummy voltage is applied in a word line setup section or a bit line setup section following the word line setup section in order to improve performance and decrease power consumption by eliminating a preconditioning current (Ray, col. 25, lines 60-63).
Allowable Subject Matter
Claims 6-10 and 17 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
9/30/2026
/E.R.A./Examiner, Art Unit 2824
9/29/2026
