Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed February 10, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 14, 18
b. Pending: 1-20
Claims 1, 14, and 18 have been amended.
Specification
The new title has been reviewed and accepted by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. On page 3, independent claim 1 recites the following in the second and third limitations, respectively:
“apply the dummy voltage to dummy word lines”
“first and second ones of the dummy word lines are adjacent to opposing ends in a vertical direction of a memory NAND string”.
However, it is unclear from the claim language whether “the dummy voltage” is applied to the “first and second ones of the dummy word lines”. The language of phrase A is broad enough that a reasonable interpretation would be that the dummy voltage is applied to some but not all dummy word lines. The claim language does not indicate that the same dummy volt is applied to all dummy word lines, and does not indicate whether there are two or more than two dummy word lines in the memory device. Thus, the dummy voltage determined “from at least a first dummy voltage and a second dummy voltage” may be applied to dummy word lines other than the “first and second ones”; the claim language does not require that the same dummy voltage must be applied to two dummy word lines that are at opposite ends of a string.
Independent claim 14 contains a fourth limitation on page 6 that recites mostly the same matter as the second and third limitation of claim 1, which are rejected under 112(b) for the above reasons. Independent claim 1, independent claim 14, and dependent claims 2-13 and 15-17, which depend upon claims 1 and 14, respectively, are thus rejected under 35 U.S.C. 112(b).
Response to Arguments
Applicant's arguments filed February 10, 2026 have been fully considered but they are not persuasive. Please see below for Examiner’s response to each argument:
Regarding the 35 U.S.C. 102 rejection of claim 1 using Hosono (US Pub. 20150262681 A1):
On page 11, Attorney argues that Hosono does not describe applying the same dummy voltage to both dummy word lines WLDS1 and WLDBS (with reference to Figs. 4A and 4D of Hosono). This argument is not convincing because based on the wording of amended claim 1, the reference must teach two dummy word lines with the same applied voltage, and must also teach two dummy word lines on opposite ends of the stack. See the 112(b) rejection of claim 1 above. In Fig. 4A of Hosono, WLDD0 and WLDD1 ([0114]) have same voltage (6V). Also in Fig. 4A, another dummy word line, WLDBD ([0099]) is located on the opposite end of the stack from WLDD0 and WLDD1.
On page 11, Attorney also argues that Hosono does not describe "the first dummy voltage corresponds to a first location of the selected word line, the second dummy voltage corresponds to a second location of the selected word line different from the first location". This argument is not convincing because Hosono teaches this limitation in paras. [0114] and [0121] in combination with Figs. 4A and 4C. Please see 102 rejection below.
Regarding the 35 U.S.C. 102 rejection of claim 18 using Hosono:
On page 11, Attorney argues that Hosono does not describe the second or third limitations of amended claim 18. Regarding the second limitation of claim 18, this argument is not convincing because Hosono does teach the second limitation of claim 18, which is mostly the same as the second limitation of claim 1. See response 1.b. above.
Examiner agrees that Hosono does not teach the third limitation of claim 18. However, Nam et al. (KR 20180021964 A; “Nam”) does teach the third limitation of claim 18. Please see 103 rejection of claim 18 below.
Regarding the 35 U.S.C. 103 rejection of claim 14 using Hosono and Costa (US Pub. 20180322935 A1):
On page 12, Attorney argues that Costa does not teach dummy word lines that are "adjacent to opposing ends in a vertical direction of a memory NAND string including the memory cell". This argument is not convincing because the dummy word lines of Costa Fig. 4C are indeed adjacent to opposing ends of a string. Specifically, Costa’s dummy word lines are immediately adjacent to drain- and source-side select lines. Similarly, in Fig. 5 of the present application, the dummy word lines WL1 and WL8 are adjacent to drain- and source-side select lines. Please see the rejection of claim 14 below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Hosono (US Pub. 20150262681 A1) with support from Micheloni et al. (Architectural and Integration Options for 3D NAND Flash Memories (2017). Computers, 6(3), 27. https://doi.org/10.3390/computers6030027).
Regarding independent claim 1, Hosono discloses a memory device (Fig. 1: memory system 100; [0038]) comprising:
a memory cell that is configured to have data stored therein (Fig. 3: memory cell MC0; [0067]; per [0004]-[0006], Figs. 1-3 all describe a first embodiment); and
a control logic (Fig. 1: memory controller 2; [0084]) that is configured to determine a dummy voltage from at least a first dummy voltage and a second dummy voltage based on a location of a selected word line electrically connected to the memory cell, and is configured to apply the dummy voltage to dummy word lines ([0114]: To dummy word lines WLDD0, WLDD1, WLDS0, and WLDS1, voltages are applied as follows. When the select word line is distant from these dummy word lines by more than .+-.3, a predetermined voltage (for example, VPASS3) is applied thereto. When the select word line is in a range of the select word line.+-.3, any voltage of 10 V, 6V, and 2 V may be applied thereto according to the distance from the select word line; [0196]: when the dummy word lines WLDBD and WLDBS are adjacent to the select word line WL, the internal voltage generating circuit 18 changes the voltage supplied to the dummy word lines WLDBD and WLDBS from the voltage VPASS4 (7 V), which is originally applied, to the voltage VPASS1 (10 V); in a description of the write operation of the third embodiment, per [0193]: the write operation in which the word line WL20 is selected and the write operation on the memory cells MC0 to MC19 and the memory cells MC27 to MC 47 which are not illustrated are the same as those of the first and second embodiments; [0190]: the configurations of the third embodiment are the same as those of the first and second embodiments. Examiner concludes that the descriptions of varying the top dummy word lines in [0114] and of varying the bottom dummy word lines in [0196] may both refer to the third embodiment of the write operation), wherein the first dummy voltage (Fig. 4A: 7V is applied to WLDBS, thus 7V may be the first dummy voltage; [0114]) corresponds to a first location of the selected word line (first location may be WL20, which is four word lines away from WLDBS), the second dummy voltage (Fig. 4C: 9V is applied to WLDBS; [0121]) corresponds to a second location of the selected word line different from the first location (second location may be WL22, which is two word lines away from WLDBS), and
wherein first (Fig. 3: dummy word line WLDS1; [0114]) and second ones of the dummy word lines (dummy word line WLDBS; [0099]) are adjacent to opposing ends in a vertical direction of a memory NAND string (Fig. 3: String-0, or per [0066]: memory string MS0. Examiner asserts that per the Abstract and Introduction sections of Micheloni, it is known in the art that BiCS memory uses a NAND structure) including the memory cell (MC0; per Fig. 3, WLDS1 and WLDBS are located at opposite ends of String-0, see annotated image below), respectively.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) as applied to claim 1 above, and further in view of Fastow (US Pub. 20190043591 A1).
Regarding claim 2, Hosono discloses the limitations of claim 1, and further through Hosono:
wherein the memory NAND string is on a substrate and
Hosono does not disclose:
comprises a multi-stack structure that includes a first stack and a second stack on the first stack,
wherein the first stack is between the second stack and the substrate, and
wherein third and fourth ones of the dummy word lines are adjacent to a junction between the first stack and the second stack.
However, Fastow teaches:
comprises a multi-stack structure (Fig. 3: floating gate NAND memory array architecture 300; [0046]) that includes a first stack (bottom deck 360; [0046]) and a second stack (top deck 310; [0046]) on the first stack,
wherein the first stack is between the second stack and the substrate (per Fig. 3, the bottom deck 360 is between the top deck 310 and the source connection 303; [0046]; [0038]: memory cells 103 may be stacked over some other memory cells 103 in multiple levels over a substrate (e.g., a semiconductor substrate) of memory device 100, forming pillars), and
wherein third and fourth ones of the dummy word lines are adjacent to a junction between the first stack and the second stack (per Fig. 3, one of the two interface dummy WLs 317 and one of the two interface dummy WLs 351 are adjacent to poly plug 350; [0047]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fastow to Hosono wherein there is a multi-stack structure that includes a first stack and a second stack on the first stack, wherein the first stack is between the second stack and the substrate, and wherein third and fourth ones of the dummy word lines are adjacent to a junction between the first stack and the second stack in order to reduce block size and operate each deck independently without creating disturbances (Fastow, [0024]).
Regarding claim 3, Hosono discloses the limitations of claim 2, and further through Hosono:
wherein the control logic (Fig. 1: 2) is configured to determine the dummy voltage based on the location of the selected word line ([0114]; [0196]; [0193]; [0190])
Hosono does not disclose:
determine the dummy voltage based on the location of the selected word line in one of the first or second stacks.
However, Fastow teaches:
determine the dummy voltage based on the location of the selected word line in one of the first or second stacks (in reference to Fig. 4, per [0056]: As regards interfacial dummy WLs 451, belonging to the selected bottom deck, they may be biased so as to form a graded transition region between the active WLs of the selected and unselected decks. Thus, in this example, their voltage bias may be, for example, between 0V (that of the active WLs of the bottom deck) and 2.0V, as shown, which transitions up to the 5-7V to float that the upper active WLs are biased at. Moreover, in embodiments, the edge dummy WLs of the selected deck may be biased so as to form a graded transition between the select gate and the active WLs).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fastow to modified Hosono wherein the dummy voltage is determined based on the location of the selected word line in one of the first or second stacks in order to reduce block size and operate each deck independently without creating disturbances (Fastow, [0024]).
Regarding claim 4, Hosono discloses the limitations of claim 2. Hosono discloses that the control logic determines dummy voltages based on the location of the selected word line.
Hosono does not disclose:
determine the dummy voltage based on the location of the selected word line in one of the first or second stacks.
However, Fastow teaches:
determine the dummy voltage based on the location of the selected word line in one of the first or second stacks (per Fig. 4 and [0056], depending on the location of the selected word line in either the bottom deck or top deck, the dummy voltage would either be 0-2V or would be floating at 5-7V).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Fastow to modified Hosono wherein the dummy voltage is determined based on the location of the selected word line in one of the first or second stacks in order to reduce block size and operate each deck independently without creating disturbances (Fastow, [0024]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) and Fastow (US Pub. 20190043591 A1) as applied to claim 4 above, and further in view of Joo et al. (US Pub. 20120307561 A1; “Joo”).
Regarding claim 5, Hosono and Fastow together disclose the limitations of claim 4. Hosono discloses that the control logic determines dummy voltages based on the location of the selected word line.
Also, Fastow discloses:
wherein, in a case of Top-to-Bottom (T2B) programming (in reference to Fig. 6, per [0063]: In embodiments with two decks, the programming sequence may, for example, progress from poly plug 659 outward towards drain 601, in the case of the top deck program 640, or downwards towards source 660, as in the case of bottom deck program 630. Examiner concludes that bottom deck programming is analogous to T2B programming),
Neither Hosono nor Fastow disclose:
the control logic is configured to apply the dummy voltage having a first voltage when the selected word line is located in the first stack, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the selected word line is located in the second stack.
However, Joo teaches:
the control logic is configured to apply the dummy voltage (per [0062], the access circuit 22 applies dummy word line signals to the dummy word lines; [0067]: The control logic 50 controls the overall operation of the access circuit 22) having a first voltage when the selected word line is located in the first stack (per Fig. 15 and [0110], WL7 is selected, which per Fig. 14 is in the first, or lower, stack; also per Fig. 15, intermediate dummy word line DWL1 has the second dummy word line voltage VDUM2, which is higher than the first dummy word line voltage VDUM1), and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the selected word line is located in the second stack (per Fig. 16, WL12 is selected, which per Fig. 14 is in the second, or upper, stack; also per Fig. 16, intermediate dummy word line DWL1 has the first dummy word line voltage VDUM1, which is lower than the second dummy word line voltage VDUM2).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Joo to modified Hosono wherein the control logic is configured to apply the dummy voltage having a first voltage when the selected word line is located in the first stack, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the selected word line is located in the second stack in order to prevent a decrease in read margin due to disturbance and improve the operating characteristics of the non-volatile memory device (Joo, [0006]).
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) as applied to claim 1 above, and further in view of Shim et al. (US Pub. 20170062065 A1; “Shim”).
Regarding claim 11, Hosono discloses the limitations of claim 1. Hosono discloses control logic and a memory cell, but does not disclose:
wherein the control logic is configured to determine the dummy voltage based on a program/erase cycle (P/E cycle) or a temperature of the memory cell.
However, Shim teaches:
wherein the control logic is configured to determine the dummy voltage based on a program/erase cycle (P/E cycle) or a temperature of the memory cell ([0026]: the dummy pulse controller may cause the voltage generator to apply the dummy pulse to at least some of the memory blocks based on at least one of a number of a program/erase cycle of the first memory block, an elapsed time from a completion of the program loop and an operating temperature of the nonvolatile memory device).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Shim to modified Hosono wherein the control logic is configured to determine the dummy voltage based on a program/erase cycle (P/E cycle) or a temperature of the memory cell in order to reduce the number of error bits in a read operation by applying a dummy pulse to memory blocks before the read operation (Shim, [0030] & [0203]).
Regarding claim 12, Hosono and Shim together disclose the limitations of claim 11. Hosono discloses control logic and a memory cell. Hosono does not disclose:
wherein the control logic is configured to apply the dummy voltage having a first voltage when the P/E cycle of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the P/E cycle of the memory cell is lower than the first reference value.
However, Shim teaches:
wherein the control logic is configured to apply the dummy voltage ([0026]) having a first voltage when the P/E cycle of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the P/E cycle of the memory cell is lower than the first reference value ([0149]: The dummy pulse control signal generator 600 may apply the dummy pulse control signal DPC to one of the high voltage generator 710 and the low voltage generator 730 based on at least one of the first counting value CV1, the second counting value CV; [0132]: The program/erase cycle counter 540 counts a number of program/erase cycle on the selected memory cells based on the decoded command D_CMD and the row address R_ADDR and provides the dummy pulse controller 600 with a first counting value CV1. The first counting value CV1 indicates the counted number of the program/erase cycle on the selected memory cells; [0150]: The high voltage generator 710 may periodically apply the read pass voltage VRPASS as the dummy pulse DP to at least some of the memory blocks BLK1˜BLKz in response to the dummy pulse control signal DPC. The low voltage generator 730 may periodically apply the read voltage VRD as the dummy pulse DP to at least some of the memory blocks BLK1˜BLKz in response to the dummy pulse control signal DPC. Examiner concludes that CV1 is a first reference value and that when CV1 is higher than a number, the dummy voltages may be high and vice versa).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Shim to modified Hosono wherein the control logic is configured to apply the dummy voltage having a first voltage when the P/E cycle of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage lower than the first voltage when the P/E cycle of the memory cell is lower than the first reference value in order to reduce the number of error bits in a read operation by applying a dummy pulse to memory blocks before the read operation (Shim, [0030] & [0203]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) and Shim (US Pub. 20240220142 A1) as applied to claim 11 above, and further in view of Nam (KR 20180021964 A).
Regarding claim 13, Hosono and Shim together disclose the limitations of claim 11. Hosono discloses control logic, a dummy voltage, and a memory cell.
Neither Hosono nor Shim explicitly disclose:
wherein the control logic is configured to apply the dummy voltage having a first voltage when the temperature of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage higher than the first voltage when the temperature of the memory cell is lower than the first reference value.
However, Nam teaches:
wherein the control logic (Fig. 1: dummy word line pre-pulse controller (DWLPC) within control logic circuit 119) is configured to apply the dummy voltage ([0068]: a pre-pulse (VDP) applied to dummy memory cells) having a first voltage (first voltage in screenshot of Fig. 13 below) when the temperature of the memory cell is higher than a first reference value (first reference value in screenshot below), and is configured to apply the dummy voltage (VDP) having a second voltage (second voltage in screenshot below) higher than the first voltage when the temperature of the memory cell is lower than the first reference value.
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It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Nam to modified Hosono wherein the control logic is configured to apply the dummy voltage having a first voltage when the temperature of the memory cell is higher than a first reference value, and is configured to apply the dummy voltage having a second voltage higher than the first voltage when the temperature of the memory cell is lower than the first reference value in order to reduce the amount of stress applied to the memory cells of the unselected cell strings and improving the reliability of data written to the memory cells (Nam, [0048]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) in view of Costa (US Pub. 20180322935 A1).
Independent claim 14 contains limitations that are substantially the same as independent claim 1, and those limitations are thus rejected for the same reasons using Hosono.
Hosono does not disclose:
apply a verification voltage to a selected word line electrically connected to the memory cell during a verifying period for verifying the memory cell;
apply a dummy voltage from at least a first dummy voltage and a second dummy voltage based on a location of the selected word line to dummy word lines during the verifying period, and first and second ones of the dummy word lines are adjacent to opposing ends in a vertical direction of a memory NAND string including the memory cell, respectively; and
apply a verification pass voltage to unselected word lines other than the dummy word lines during the verifying period.
However, Costa teaches:
apply a verification voltage to a selected word line electrically connected to the memory cell during a verifying period for verifying the memory cell ([0036]: In one embodiment, the system applies a pass voltage to the subset of memory cells that is dependent upon the reference voltage applied to the selected word line….the system may use a lower pass voltage for the subset of memory cells when applying a higher read or verify reference voltage to a selected word line and a higher pass voltage when applying a lower read or verify reference voltage; [0167]: Step 712 includes setting a read reference voltage or verify reference voltage for the selected word line during the sense phase corresponding to a state being read or verified; [0193]: applying a verify voltage to a first selected word line…applying the verify voltage to a second selected word line…applying the verify voltage to a third selected word line);
apply a dummy voltage from at least a first dummy voltage and a second dummy voltage based on a location of the selected word line to dummy word lines during the verifying period ([0097]: During a read or verify process, the unselected memory cells and dummy word lines are provided with one or more read pass voltages at their control gates so that these memory cells will operate as pass gates (e.g., conducting current regardless of whether they are programmed or erased)), and first and second ones of the dummy word lines (Fig. 4C: dummy word line layers DWLL1a and DWLL2a; [0070]) are adjacent to opposing ends in a vertical direction (per Fig. 4C, dummy word line layer DWLL1a is adjacent to the drain end and dummy word line layer DWLL2a is adjacent to the source end; [0070]: Other embodiments can implement more or less than four drain side select layers, more or less than four source side select layers, more or less than four dummy word line layers, and more or less than forty eight word line layers. Examiner asserts that the quoted part of para. [0070] and the three dots in the middle of Fig. 4C support the fact that the dummy word lines of Costa are adjacent to opposing ends) of a memory NAND string including the memory cell ([0072]: memory cells are arranged in NAND strings), respectively; and
apply a verification pass voltage to unselected word lines other than the dummy word lines during the verifying period ([0097]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Costa to modified Hosono wherein a verification voltage is applied to a selected word line electrically connected to the memory cell during a verifying period for verifying the memory cell; a dummy voltage from at least a first dummy voltage and a second dummy voltage based on a location of the selected word line is applied to dummy word lines during the verifying period, and first and second ones of the dummy word lines are adjacent to opposing ends in a vertical direction of a memory NAND string including the memory cell, respectively; and a verification pass voltage is applied to unselected word lines other than the dummy word lines during the verifying period in order to reduce errors and narrow the threshold voltages for logic states (Costa, [0029] & [0031]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) and Costa (US Pub. 20180322935 A1) as applied to claim 14 above, and further in view of Hwang (US Pub. 20220328101 A1).
Regarding claim 15, Hosono and Costa together disclose the limitations of claim 14. Hosono discloses control logic and a dummy voltage.
Neither Hosono nor Costa explicitly disclose:
apply the dummy voltage in a word line setup section of the verifying period.
However, Hwang teaches:
apply the dummy voltage in a word line setup section of the verifying period (per Fig. 8, a voltage is applied to dummy word line CPWL during the Verify Phase, and during this time, voltages are applied to the word lines WLs; [0113]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hwang to modified Hosono wherein the dummy voltage is applied in a word line setup section of the verifying period in order to improve the reliability of operations on a memory block (Hwang, [0093]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) and Costa (US Pub. 20180322935 A1) as applied to claim 14 above, and further in view of Ray (US Pat. 9704588 B1).
Regarding claim 16, Hosono and Costa together disclose the limitations of claim 14. Hosono discloses control logic and a dummy voltage.
Neither Hosono nor Costa explicitly disclose:
apply the dummy voltage in a bit line setup section of the verifying period.
However, Ray teaches:
apply the dummy voltage in a bit line setup section of the verifying period (per Fig. 10, a voltage Vread is applied to the Dummy WL while the selected BL is being charged; col. 19, lines 35-36: FIG. 10 is a timing diagram describing waveforms during a read or verify operation according to one embodiment).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ray to modified Hosono wherein the dummy voltage is applied in a bit line setup section of the verifying period in order to improve performance and decrease power consumption by eliminating a preconditioning current (Ray, col. 25, lines 60-63).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) in view of Nam (KR 20180021964 A).
Independent claim 18 contains a second limitation that is nearly identical in claimed subject matter as part of the second limitation of claim 1. The second limitation is thus rejected for the same reasons as independent claim 1.
Hosono further discloses a memory device operating method ([0088]: The control circuit 15 controls the overall operation of the non-volatile semiconductor memory device. That is, The control circuit 15 performs a write sequence of a write operation of data based on a control signal, a command, and an address supplied from the address-command register 17) comprising:
applying a verification voltage to a selected word line ([0102]: During a write operation, when the non-volatile semiconductor memory device receives write data and starts the write operation, a write cycle including a write pulse application operation and a write verification operation is performed, and the write cycle is repeated until simultaneous write operations of plural memory cells are finished; [0099]: The internal voltage generating circuit 18 supplies the voltage VPGM to the select word line WL. Examiner concludes that the write operation, which includes verification, is performed on a selected word line) electrically connected to a memory cell having data stored therein (in reference to Fig. 1, per [0041]: the memory string MS includes plural memory cells MC that are connected in series to each other, and the above-described word lines WL are connected to a control gate CG included in the memory cell MC);
Hosono does not disclose:
applying the dummy voltage to dummy word lines located at an upper end and a lower end of a memory NAND string including the memory cell, respectively.
However, Nam teaches:
applying the dummy voltage to dummy word lines located at an upper end and a lower end of a memory NAND string including the memory cell ([0074]: As illustrated in FIG. 7…the same pre-pulse (VDP) is applied to the first and second dummy memory cells (DMC1, DMC2); in reference to Fig. 2, per [0026]: Each cell string may include…a first dummy memory cell (DMC1) connected to a first dummy word line (DWL1)…a second dummy memory cell (DMC2) connected to a second dummy word line (DWL2)), respectively.
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Nam to modified Hosono wherein the operating method comprises applying the dummy voltage to dummy word lines located at an upper end and a lower end of a memory NAND string including the memory cell in order to reduce the amount of stress applied to the memory cells of the unselected cell strings and improving the reliability of data written to the memory cells (Nam, [0048]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hosono (US Pub. 20150262681 A1) as applied to claim 18 above, and further in view of Ray (US Pat. 9704588 B1).
Regarding claim 20, Hosono discloses the limitations of claim 18. Hosono discloses applying a dummy voltage, but does not disclose:
applying the dummy voltage in a word line setup section or a bit line setup section following the word line setup section.
However, Ray teaches:
applying the dummy voltage in a word line setup section (per Fig. 10, Vread is applied to the Dummy WL while Selected WL is charged to Vread) or a bit line setup section following the word line setup section (see rejection of claim 16 above; the peak voltage, Vpre, on the Selected BL occurs after the selected WL is charged with Vread).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ray to modified Hosono wherein the dummy voltage is applied in a word line setup section or a bit line setup section following the word line setup section in order to improve performance and decrease power consumption by eliminating a preconditioning current (Ray, col. 25, lines 60-63).
Allowable Subject Matter
Claims 6-10 and 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Higashitani (US Pub. 20110188313 A1): para. [0106] and Fig. 13 are relevant to claims 1, 14, and 18.
Kim et al. (US Pub. 20110222339 A1): para. [0067] and Fig. 6 are relevant to claims 1, 14, and 18.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824 4/20/2026
/E.R.A./Examiner, Art Unit 2824
4/18/2026
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