DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I: Claims 1-11 in the reply filed on 06/09/2026 is acknowledged. Claims 12-20 are hereby withdrawn as being related to nonelected inventions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6, 8 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0175199 A1 to Song et al. (hereinafter “Song”).
Regarding claim 1, Song discloses a semiconductor package, comprising:
a first semiconductor chip (wafer-level semiconductor die 200 having IC 210; Fig. 1; paragraph [0027]);
a connection die adjacent a side surface of the first semiconductor chip (wafer-level semiconductor die 300 not having IC and adjacent side surface of die 200; Fig. 1; paragraph [0032]); and
a second semiconductor chip on the first semiconductor chip and the connection die (wafer-level semiconductor die 400 on die 200 and die 300; Fig. 1; paragraph [0042]), wherein the first semiconductor chip includes a plurality of first through electrodes, wherein the connection die includes a plurality of second through electrodes (die 200 comprises conductive portions 230 including through electrodes and die 300 comprises conductive portions 330 including through electrodes; Figs. 1-2; paragraphs [0030], [0035]), and wherein the first through electrodes and the second through electrodes are below and vertically overlap the second semiconductor chip (conductive portions 230, 330 including through electrodes are below and vertically overlap with die 400; Fig. 1).
Regarding claim 2, Song discloses the semiconductor package of claim 1, wherein the first semiconductor chip includes a circuit layer, and the connection die does not include a circuit layer (die 200 includes IC 210 and die 300 does not; Fig. 1; paragraphs [0027], [0032]).
Regarding claim 3, Song discloses the semiconductor package of claim 1, wherein the plurality of first through electrodes each have a first diameter, the plurality of second through electrodes each have a second diameter, and the first diameter is smaller than the second diameter (conductive portions 230 may include a pad portion having a first diameter that is smaller than the pad portion of the conductive portions 330; Fig. 2).
Regarding claim 6, Song discloses the semiconductor package of claim 1, further comprising a dummy die on the first semiconductor chip, wherein the second semiconductor chip is on an outer section of the first semiconductor chip, and wherein the dummy die is on a central section of the first semiconductor chip (interconnection layer 220 disposed on central portion of die 200 and die 400 disposed on outer portions of die 200; Fig. 1).
Regarding claim 8, Song discloses the semiconductor package of claim 6, wherein the first semiconductor chip further includes a plurality of first dummy pads in or on an upper portion thereof (die 200 comprising conductive pads at upper portion thereof; Fig. 1), the dummy die includes a plurality of second dummy pads in or on a lower portion thereof (interconnection layer 220 includes plurality of conductive pads at lower portion; Fig. 1), and the semiconductor package further comprises a plurality of heat transfer terminals between the first dummy pads and the second dummy pads (semiconductor package comprises vias between each of the conductive pads; Fig. 1).
Regarding claim 10, Song discloses the semiconductor package of claim 1, further comprising a third semiconductor chip on the first semiconductor chip, wherein the second semiconductor chip is on an outer section of the first semiconductor chip, the third semiconductor chip is on a central section of the first semiconductor chip (second die 200 stacked over central portion of first die 200 and die 400 stacked over outer portions of first die 200; Fig. 9), the first semiconductor chip further includes a plurality of third through electrodes, and the third through electrodes are below and vertically overlap the third semiconductor chip (third conductive portions 230 including through electrodes are below and vertically overlap second die 200; Fig. 9).
Regarding claim 11, Song discloses the semiconductor package of claim 1, wherein the first semiconductor chip further includes a plurality of first wiring layers that are connected to the first through electrodes and are vertically stacked (die 200 includes plurality of interconnection layers stacked over and connected to conductive portions 230 including through electrodes; Fig. 1), the connection die further includes a plurality of second wiring layers that are connected to the second through electrodes and are vertically stacked (die 300 includes plurality of interconnection layers stacked over and connected to conductive portions 330 including through electrodes; Fig. 1), and a number of the stacked first wiring layers is greater than a number of the stacked second wiring layers (greater number of interconnection layers associated with die 200 than with die 300; Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Song.
Regarding claim 4, Song discloses the semiconductor package of claim 1, wherein the plurality of first through electrodes are arranged at a first pitch, the plurality of second through electrodes are arranged at a second pitch, and the first pitch is similar to the second pitch (conductive portions 230 have same pitch as conductive portions 330; Fig. 1).
Song fails to explicitly disclose the first pitch is smaller than the second pitch.
However, Song already discloses different widths of the conductive portions 230, 330 (see Figs. 1-2).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Song in this manner in order to potentially provide higher interconnect density for smaller pitch and improved current-carrying capacity for larger pitch. Further, such a configuration is not novel in the art as evidenced by US 2021/0193640 A1 to Song et al. (see pitch of through electrodes of chips 100, 300 in Fig. 1).
Regarding claim 5, Song discloses the semiconductor package of claim 1, wherein the second semiconductor chip is a logic chip, and the first semiconductor chip is a memory chip (die 200 may be a memory chip and die 400 may be a logic chip; paragraphs [0027], [0042]).
Song fails to explicitly disclose the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.
However, Song already discloses the first and second chips including memory and logic chips.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Song in this manner in order to potentially provide increased power delivery from package substrate with a logic chip at a bottom position and reduces the number of power vias required to be disposed through the stack.
Regarding claim 7, Song discloses the semiconductor package of claim 6, wherein the connection die comprises a plurality of connection dies and the second semiconductor chip comprises a plurality of second semiconductor chips (plurality of dies 300 and plurality of dies 400; Fig. 17), the second semiconductor chips are spaced apart in a first direction from each other with the dummy die thereabove (dies 400 spaced apart in first direction with interconnection layer 200 thereabove; Fig. 17), the connection dies are spaced apart in the first direction from each other with the first semiconductor chip thereabove (dies 300 spaced apart in first direction with die 200 thereabove; Fig. 17), and a spacing distance between the second semiconductor chips is smaller than a spacing distance between the connection dies (smaller spacing between dies 400 than between dies 300; Fig. 16).
Song fails to explicitly disclose the dummy die therebetween and the first chip therebetween.
However, Figs. 8 and 9 Song already discloses interconnection layers between dies 200 and between dies 300.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Song in this manner in order to potentially provide thermal spreading and hotspot reduction.
Regarding claim 9, Song discloses the semiconductor package of claim 6, further comprising a heat transfer layer above the first semiconductor chip and the dummy die, wherein the heat transfer layer includes a thermal interface material (TIM) (adhesion film including thermal interface material disposed above die 200 and interconnection layer 220; Fig. 10; paragraph [0075]).
Song fails to explicitly disclose the heat transfer layer between the first semiconductor chip and the dummy die.
However, Figs. 8 and 9 Song already discloses the thermal interface material.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Song in this manner in order to potentially provide thermal spreading and hotspot reduction.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2019/0378795 A1 to Lee et al. which discloses related semiconductor packages.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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