Prosecution Insights
Last updated: July 17, 2026
Application No. 18/485,415

PORE DEVICE AND FINE PARTICLE MEASUREMENT SYSTEM

Non-Final OA §102§103
Filed
Oct 12, 2023
Priority
Oct 14, 2022 — JP 2022-165568
Examiner
WEST, PAUL M
Art Unit
2855
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advantest Corporation
OA Round
3 (Non-Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
851 granted / 1010 resolved
+16.3% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
21 currently pending
Career history
1022
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
69.3%
+29.3% vs TC avg
§102
8.8%
-31.2% vs TC avg
§112
15.5%
-24.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1010 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8 May 2026 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 4, 7, 10, 13 and 14 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Miki et al. (US 2016/0320286). Regarding claims 1 and 13, Miki et al. disclose a pore device used together with a measurement device 200, the pore device comprising: a pore chip (110 or 10); a chamber (21,22) partitioned by the pore chip (see Fig. 10 and par. 0089, partitioned at wall 31); a measurement terminal group (13a,13b) structured to apply an electric signal to the chamber from the measurement device and/or to output an electric signal generated in the chamber to the measurement device 200 (see pars. 0067-0068, chips 10 such as one in Fig. 10, are examples of the chip 110 that is generically shown in Figs. 1-6; see Fig. 1 and pars. 0041 and 0043, describing chip with micropore and electrodes where determination device 200 applies voltage to and reads voltage from electrodes of chip); a nonvolatile memory 120 (par. 0042); and interface means 300 connected to the nonvolatile memory such that the nonvolatile memory is accessible from an outside of the pore device (par. 0040), wherein the non-volatile memory is writable with a use history of the pore device to be read out when the pore device is collected by its manufacturer, and the use history of the pore device includes measurement conditions, wherein the measurement conditions include at least one of an applied voltage, particles to be used, a serial number and version information of the measurement device (see pars. 0042 and 0048; the memory is written with an indication of whether it is used which is a usage history, and it is capable of being read out when the pore device is collected by anyone included its manufacturer; the memory 120 can be a RAM or a flash RAM which is a memory that is writable with many types of data including numbers that represent measurement conditions, voltage, or a serial number). Note that the limitation “writable with a use history” that “includes measurement conditions” only requires that the memory be capable of being written with these values and is deemed to be met by the disclosure of a RAM or flash RAM because RAM is capable of being written with data that indicates measurement conditions. Regarding claim 4, Miki et al. disclose that the interface means 300 includes a plurality of terminals to be coupled to a memory interface of the measurement device to the nonvolatile memory (see par. 0040 and Figs. 1 and 3). Regarding claims 7 and 14, Miki et al. disclose a fine particle measurement system comprising: a pore device 100; and a measurement device 200, wherein the pore device includes: a pore chip (110 or 10); a chamber (21,22) partitioned by the pore chip (see Fig. 10 and par. 0089, partitioned at wall 31); a measurement terminal group (13a,13b) structured to apply an electric signal to the chamber from the measurement device and/or to output an electric signal generated in the chamber to the measurement device 200 (see pars. 0067-0068, chips 10 such as one in Fig. 10, are examples of the chip 110 that is generically shown in Figs. 1-6; see Fig. 1 and pars. 0041 and 0043, describing chip with micropore and electrodes where determination device 200 applies voltage to and reads voltage from electrodes of chip); a nonvolatile memory 120 (par. 0042); and interface means 300 connected to the nonvolatile memory such that the nonvolatile memory is accessible from an outside of the pore device (par. 0040), wherein the non-volatile memory is writable with a use history of the pore device to be read out when the pore device is collected by its manufacturer, and the use history of the pore device includes measurement conditions, wherein the measurement conditions include at least one of an applied voltage, particles to be used, a serial number and version information of the measurement device (see pars. 0042 and 0048; the memory is written with an indication of whether it is used which is a usage history, and it is capable of being read out when the pore device is collected by anyone included its manufacturer; the memory 120 can be a RAM or a flash RAM which is a memory that is writable with many types of data including numbers that represent measurement conditions, voltage, or a serial number). Note that the limitation “writable with a use history” that “includes measurement conditions” only requires that the memory be capable of being written with these values and is deemed to be met by the disclosure of a RAM or flash RAM because RAM is capable of being written with data that indicates measurement conditions. Regarding claim 10, Miki et al. disclose that the interface means 300 includes a plurality of terminals to be coupled to a memory interface of the measurement device to the nonvolatile memory (see par. 0040 and Figs. 1 and 3). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2, 6, 8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miki et al. (US 2016/0320286) in view of Naono (US 2022/0317016). Regarding claims 2 and 8, Miki et al. do not disclose the nonvolatile memory being structured to store unique information of the pore device in advance of shipment of the pore device. Naono discloses a pore device 200 with a pore chip (230,241), a measurement chamber (210,220) partitioned by the pore chip, and a nonvolatile memory 390 (par. 0095, means 390 may be semiconductor memory), wherein the nonvolatile memory is structured to store unique information of the pore device in advance of shipment of the pore device, and wherein a corresponding measurement device 120,140 is structured to read the unique information from the nonvolatile memory and automatically set measurement conditions in accordance with the unique information (pars. 0094-0096, semiconductor memory stores unique sensor ID; pars. 0172-0178). It would have been obvious to one of ordinary skill in the art to have to have employed the teachings of Naono, of including a unique sensor ID in the nonvolatile memory and reading this information with the measurement device, in the device and system of Miki et al., because it would have provided an efficient way to keep track of individual sensor modules/chips and their particular features and histories, and it would have provided information useful more accurately making particle measurements with the sensor chip device. Regarding claims 6 and 12, Miki et al. disclose the pore device further comprising: a contact sheet 115 on which the nonvolatile memory 120 and the interface means are mounted (see Figs. 4 and 5), and also on which the pore chip 110 is mounted. Miki et al. do not disclose a pore chip case structured to house the pore chip and that is bonded to the contact sheet. Naono discloses using a pore chip case 300 for housing a pore chip (par. 0094 and Fig. 3). It would have been obvious to one of ordinary skill in the art to have used some kind of pore chip case as taught by Naono, to house the pore chip on the contact sheet of Miki et al., because it would have provided protection and support structure for the pore chip and its elements. Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miki et al. (US 2016/0320286) in view of McKirdy (US 2019/0271681). Regarding claims 5 and 11, Miki et al. do not disclose the interface means, and the nonvolatile memory constituting a radio frequency (RF) tag, and the RF tag being accessible from a reader and writer of the measurement device in a non-contact manner. McKirdy discloses a microfluidic chip device (Fig. 11) used together with a measurement device (par. 0090, interface device with RFID sensor reader) wherein the microfluidic chip includes a nonvolatile memory (RFID element in Fig. 11) and wherein an interface with the nonvolatile memory and the measurement device constitutes a RF tag (Fig. 11) and the RF tag is accessible from a reader and writer of the measurement device in a non-contact manner (par. 0090). It would have been obvious to one ordinary skill in the art to have used a RF tag type memory with RF tag reading/writing interface, as taught by McKirdy, in the device and system of Miki et al., because the RF tag would allow the memory information to be accessed by the measurement device or other devices without direct physical contact. Response to Arguments Applicant's arguments filed 8 May 2026 have been fully considered but they are not persuasive. Applicant has argued that the Miki reference does not disclose the limitation that requires a non-volatile memory that is writable with a use history of the pore device with the use history including measurement conditions. It is true that Miki does not explicitly teach writing measurement conditions to the memory 120; however, Miki teaches that the memory device can be a semiconductor memory such as a RAM or a flash RAM. This type of memory is writable with many forms of complex data including values that represent measurement conditions. The devices claimed in claims 1 and 7 only require a memory that is capable of being written with use history including measurement conditions, and any RAM has this capability. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL M WEST whose telephone number is (571)272-2139. The examiner can normally be reached M-F 9 am - 5:30 pm (CT). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kristina DeHerrera can be reached at 303-297-4237. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PAUL M. WEST/Primary Examiner, Art Unit 2855
Read full office action

Prosecution Timeline

Oct 12, 2023
Application Filed
Sep 17, 2025
Non-Final Rejection mailed — §102, §103
Dec 17, 2025
Response Filed
Mar 10, 2026
Final Rejection mailed — §102, §103
May 08, 2026
Response after Non-Final Action
Jun 04, 2026
Request for Continued Examination
Jun 10, 2026
Response after Non-Final Action
Jun 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12680907
BOUNDARY LAYER TESTING SYSTEM WITH ENHANCED ENTRY REGION FOR ANGULATED SURFACES
1y 0m to grant Granted Jul 14, 2026
Patent 12671967
SYSTEMS AND METHODS FOR WIRELESS ACTIVATION AND COMMUNICATIONS IN CONCRETE SENSORS
2y 6m to grant Granted Jun 30, 2026
Patent 12669413
POD PERFORMANCE TEST SYSTEM AND METHOD FOR NEAR SPACE AEROSTAT
2y 1m to grant Granted Jun 30, 2026
Patent 12669427
SIZE-TUNABLE SYNTHETIC PARTICLES WITH TUNABLE OPTICAL PROPERTIES AND METHODS FOR USING THE SAME FOR IMMUNE CELL ACTIVATION
1y 6m to grant Granted Jun 30, 2026
Patent 12663342
Vibration Test Bench for Permanent Maglev Train
2y 6m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
98%
With Interview (+13.8%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1010 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month