DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-12 and 14-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chien et al. (US Patent Appl. Pub. No. 2005/0162927 A1).
[Re claim 11] Chien discloses the semiconductor structure, comprising: a substrate (108); a dielectric layer (112) on the substrate (108); isolation structures (104) extending through the dielectric layer (112) into the substrate (108); and a floating gate (102a and 102b) on the dielectric layer (112) and between the isolation structures (104), wherein the floating gate comprises: a first portion (102 vertical part above 112 dielectric layer) directly on the dielectric layer; and second portions (102 vertical part above 104 isolation) on sidewalls of the first portion, wherein a vertical dimension of the first portion is greater than a vertical dimension of each of the second portions (see figure 7A-7G and paragraph [0042]-[0044]).
[Re claim 12] Chien discloses the semiconductor structure wherein a width of a top portion of the floating gate (top surface of 102) is greater than a width of a bottom portion of the floating gate (bottom portion of 102) (see figure 7G).
[Re claim 14] Chien discloses the semiconductor structure wherein a top surface of the floating gate (top surface of 102) is higher than top surfaces of the isolation structures (104) (see figure 7G).
[Re claim 15] Chien discloses the semiconductor structure wherein bottom surfaces of the second portions (102 vertical part above 104 isolation) are in direct contact with top surfaces of the isolation structures (104) (see figure 7G).
[Re claim 16] Chien discloses the semiconductor structure wherein the first portion (102 vertical part above 112 dielectric layer) is in direct contact with sidewalls of the isolation structures (104) (see figure 7G).
[Re claim 17] Chien discloses the semiconductor structure wherein the first portion (102 vertical part above 112 dielectric layer) and the second portions (102 vertical part above 104 isolation) comprise a same material (polysilicon) (see paragraph [0042] and [0044]).
[Re claim18] Chien discloses the semiconductor structure further comprising: a dielectric material (110) disposed along a sidewall and a top surface of the floating gate (102) and along top surfaces of the isolation structures (104); and a control gate (106) on the dielectric material (see figure 7I-7J and paragraph [0045]-[0046]).
[Re claim 19] Chien also discloses the semiconductor structure wherein the dielectric material (ONO layer 110) comprises: a first dielectric layer (oxide layer); a second dielectric layer (nitride layer) on the first dielectric layer; and a third dielectric layer (oxide layer) on the second dielectric layer (see paragraph [0045]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chien et al. (US Patent Appl. Pub. No. 2005/0162927 A1) in view of Yamauchi et al. (US Patent No. 5,962,889).
[Re claim 13] Chien discloses the device as claimed and rejected in claim 11, but Chien does not disclose the semiconductor structure wherein the floating gate comprises rounded corners. However, Yamauchi discloses the semiconductor structure wherein the floating gate (3’) comprises rounded corners (see figure 8G and column 8 line 30-35). It would have been obvious to one of the ordinary skill in the art to the effective filing date of the instant application to the floating gate having rounded corners in the device of Chien in order to improve reliability of the device.
Allowable Subject Matter
Claim 1-10 allowed.
The following is an examiner's statement of reasons for allowance: Claim 1 allowable because of the prior art, either singly or in combination, fails to anticipate or render obvious, the method, the step of conformally forming a second conductor layer on the first conductor layer and the isolation structures; and removing horizontal portions of the second conductor layer to form a floating gate, wherein the floating gate comprises a first portion corresponding to the first conductor layer and second portions corresponding to vertical portions of the second conductor layer, wherein a vertical dimension of the first portion is greater than a vertical dimension of each of the second portions. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 2-10 depend from claim 1 so they are allowable for the same reason.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KYOUNG LEE/ Primary Examiner, Art Unit 2817
Prosecution Insights