DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “FLOATING GATE DEVICE AND METHOD FOR FORMING THE SAME”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (US Patent Appl. Pub. No. 2004/0115882 A1).
[Re claim 1] Hung discloses the method for forming a semiconductor structure, comprising: providing a substrate (100); forming a dielectric layer (102) on the substrate; forming a first conductor layer (104) on the dielectric layer (see figure 1A and paragraph [0017]-[0019]); forming isolation structures (112) on the substrate, wherein the isolation structures (112) extend through the first conductor layer (104) and the dielectric layer (102) into the substrate; removing a portion of the isolation structures (112) (see figure 1B-1C and paragraph [0021]-[0022]); conformally forming a second conductor layer (114) on the first conductor layer (104) and the isolation structures (112) (see figure 1D and paragraph [0023]); and removing horizontal portions of the second conductor layer (114) to form a floating gate (114a and 104), wherein the floating gate comprises vertical portions of the first conductor layer and the second conductor layer (see figure 1E-1F and paragraph [0024]-[0025]).
[Re claim 2] Hung discloses the method for forming a semiconductor structure wherein removing the horizontal portions of the second conductor layer (114) comprises performing an etching process on the second conductor layer (114) such that the vertical portions of the second conductor layer (114a) remain on sidewalls of the first conductor layer (104) and expose a top surface of the first conductor layer and top surfaces of the isolation structures (112) (see figure 1E-1F and paragraphs [0024]-[0026]).
[Re claim 3] Hung discloses the method for forming a semiconductor structure wherein removing the portion of the isolation structures comprises performing an etching process on the isolation structures such that top surfaces of the isolation structures are lower than a top surface of the first conductor layer (see figure 1C and paragraph [0022]).
[Re claim 4] Hung discloses the method for forming a semiconductor structure wherein the floating gate (114a comprises rounded edge) comprises rounded corners (see figure 1E-1F).
[Re claim 5] Hung discloses the method for forming a semiconductor structure wherein bottom surfaces of the vertical portions of the second conductor layer (114a) are in direct contact with top surfaces of the isolation structures (112) (see figure 1E-1F).
[Re claim 6] Hung discloses the method for forming a semiconductor structure wherein a width of a top portion (top portion of 104 with 114a) of the floating gate is greater than a width of a bottom portion (bottom portion of 104) of the floating gate (see figure 1F).
[Re claim 7] Hung discloses the method for forming a semiconductor structure wherein forming the isolation structures (112) comprises: providing a mask layer (106) as an etch mask and performing an etching process through the etch mask to form recesses, wherein the recesses extend from a top surface of the mask layer through the first conductor layer and the dielectric layer into the substrate; filling the recesses with an isolation material; and performing a planarization process (removing insulating material 112 outside the trench) to make a top surface of the isolation material coplanar with the top surface of the mask layer (see figure 1C and paragraph [0022]).
[Re claim 8] Hung discloses the method for forming a semiconductor structure wherein the first conductor layer (104) and the second conductor layer (114) comprise a same material (doped polysilicon) (see paragraph [0019] and [0023]).
[Re claim 9] Hung discloses the method for forming a semiconductor structure further comprising: conformally forming a dielectric material (116) on the floating gate (104 and 114a) and the isolation structures (112); and forming a control gate (118) on the dielectric material (see figure 1G and paragraph [0026]-[0027]).
[Re claim 10] Hung discloses the method for forming a semiconductor structure wherein the dielectric material (ONO layer 116) comprises: a first dielectric layer (oxide layer); a second dielectric layer (silicon nitride layer) on the first dielectric layer; and a third dielectric layer (oxide layer) on the second dielectric layer (see figure 1G and paragraph [0026]).
[Re claim 11] Hung discloses the semiconductor structure, comprising: a substrate (100); a dielectric layer (102) on the substrate (100) (see figure 1A and paragraph [0017]-[0019]); isolation structures (112) extending through the dielectric layer (102) into the substrate (see figure 1C and paragraph [0022]); and a floating gate (114a and 104) on the dielectric layer (102) and between the isolation structures (112), wherein the floating gate (114a and 104) comprises: a first portion (104) directly on the dielectric layer; and second portions (114a) on sidewalls of the first portion (see figure 1D-1F and paragraph [0023]-[0025]).
[Re claim 12] Hung discloses the semiconductor structure wherein a width of a top portion of the floating gate (top surface of 104 with 114a) is greater than a width of a bottom portion of the floating gate (bottom portion of 104) (see figure 1F).
[Re claim 13] Hung discloses the semiconductor structure wherein the floating gate (114a and 104) comprises rounded corners (see figure 1E-1F).
[Re claim 14] Hung discloses the semiconductor structure wherein a top surface of the floating gate (top surface of 104 with 114a) is higher than top surfaces of the isolation structures (112) (see figure 1F).
[Re claim 15] Hung discloses the semiconductor structure wherein bottom surfaces of the second portions (114a) are in direct contact with top surfaces of the isolation structures (112) (see figure 1F).
[Re claim 16] Hung discloses the semiconductor structure wherein the first portion (104) is in direct contact with sidewalls of the isolation structures (112) (see figure 1F).
[Re claim 17] Hung discloses the semiconductor structure wherein the first portion (104) and the second portions (114a) comprise a same material (doped polysilicon) (see paragraph [0019] and [0023]).
[Re claim18] Hung discloses the semiconductor structure further comprising: a dielectric material (116) disposed along a sidewall and a top surface of the floating gate (114a and 104) and along top surfaces of the isolation structures (112); and a control gate (118) on the dielectric material (see figure 1G and paragraph [0026]-[0027]).
[Re claim 19] Hung also discloses the semiconductor structure wherein the dielectric material (ONO film 9) comprises: a first dielectric layer (oxide layer); a second dielectric layer (silicon nitride layer) on the first dielectric layer; and a third dielectric layer (oxide layer) on the second dielectric layer (see figure 1G and paragraph [0026]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYOUNG LEE/Primary Examiner, Art Unit 2817