Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 4/3/2024.
Claims 1-20 are currently pending.
Claim 11 has been amended.
Claims 1-20 have been examined.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to Korean Patent Application No. 10-2022-0140510. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/12/2023 and 4/8/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
TITLE OF THE INVENTION
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Memory Devices With A Channel Thickness That Is Greater At One End and Decreases Towards the Other
OBJECTION SPECIFICATION
The disclosure is objected to because of the following informalities:
In paragraph [0078], there is a typo in the first line, which refers to Fig. 16C. As there is only Figs. 16A and 16B shown in the drawings this is assumed to be a typo.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they do not clearly and accurately show the height of T1 as described in the specification ([0104]); the dimension‑indicating lines are not correctly positioned. Specifically Fig. 18D shows the first thickness T1 appears to be thickness at the source end of the transistor that is from the top of the channel to a point in the middle of the channel in the z-direction when the channel .
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 16 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In particular the claim is unclear if the plurality of word line contacts is contacting the same gate electrode film within the plurality of semiconductor layers or if the plurality of word line contacts is contacting a portion of each gate electrode film in the plurality of semiconductor layers.
For the purposes of examination “plurality of word line contacts is contacting a portion of each gate electrode film in the plurality of semiconductor layers” will be searched for.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gomes US 20210159229 A1 (hereinafter Gomes).
Regarding claim 18, Gomes discloses:
A semiconductor memory device (Fig. 2-4B memory device with 1T-1C using a nanoribbon-based field effect transistor FET) comprising:
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array) semiconductor layer comprising a source area (Fig. 3, second S/D region314-2), a channel area (nanoribbon 304, [0049] the channel material of the nanoribbon.), and a drain area (first source 3/D region 314-1) arranged in a first horizontal direction on a substrate; (Fig. 3, base 302) the plurality of semiconductor layers being apart from one another in a second horizontal direction orthogonal to the first horizontal direction and in a vertical direction, (Fig. 4A and 4B show that the layers are further connected with would have semiconductor layers spaced apart in a second horizontal direction and in a vertical direction.) the plurality of semiconductor layers arranged in columns and rows; (an array by necessity is arranged in columns and rows which would have layers.)
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array) of cell capacitors (Fig. 2, capacitor 220 and Fig. 3, capacitor 320) extending in the first horizontal direction from the plurality of semiconductor layers, (See Fig. 4B) the plurality of cell capacitors comprising a plurality of lower electrode layers (Fig. 3, electrode 326) connected to source areas of the plurality of semiconductor layers, (Fig. 4A, [0066], a second S/D region coupled to a capacitor 420-12) a capacitor dielectric film (capacitor dielectric 330) covering the plurality of lower electrode layers, (Fig. 3, electrode 326) and an upper electrode film (electrode 328) covering the capacitor dielectric film; (See Fig. 4A.)
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array) of bit lines (Fig. 2 bit line BL 240 and Fig. 4A, bit line BL 440) extending in the vertical direction on the substrate, (See Fig. 4B) the plurality of bit lines each connected to the drain area of each of a group of semiconductor layers, (Fig. 2, the bit lines are connected to the drain of the memory device by necessity since they are part of the same memory cell of the device.) which are arranged apart from one another in the vertical direction from among the plurality of semiconductor layers, (Fig. 4A, [0066] a first S/D region coupled to the BL 440)the plurality of bit lines arranged apart from one another in the second horizontal direction; (As part of the memory array it would by necessity have bit lines that are arranged apart from each other in the horizontal direction in order to create the array.)
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array) of gate structures (Fig. 2, gate 210 and Fig. 3, gate stack 306 and Fig. 4, gate stack 406, which includes gate electrode 308 and gate dielectric 312) extending in the second horizontal direction, the plurality of gate structures (gate stack 306) surrounding the channel area(nanoribbon 304) of each of a group of semiconductor layers arranged apart from one another in the second horizontal direction from among the plurality of semiconductor layers, (As part of the memory array it would by necessary having the memory cells arranged apart from each other in the second horizontal direction.) the plurality of gate structures (gate stack 306) each including a gate dielectric film (gate dielectric 312) on the channel area (nanoribbon 304) and a gate electrode film (gate electrode 308) on the gate dielectric film; (gate dielectric 312)
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array.) of word line contacts (See Fig. 4A, gate contacts 452-11, 452-21, 452-31, 452-41) extending in the vertical direction, (See Fig. 4A) the plurality of word line contacts arranged apart from one another in the second horizontal direction, (See Fig. 4A) the plurality of word line contacts being apart from the plurality of bit lines in the first horizontal direction, (See Fig. Fig 4A, the gate contacts 452-11 are spaced apart from the bit lines 440.) each of the plurality of word line contacts connected to the gate electrode film of a corresponding one of the plurality of gate structures; (See Fig. 4A, the gate contacts 542 contact the gate stack 406 which includes the gate electrode 308 as shown in Fig. 3.)
and an insulating layer covering the plurality of semiconductor layers, the plurality of gate structures, the plurality of cell capacitors, the plurality of bit lines, and the plurality of word line contacts, on the substrate, the insulating layer filling a space between one of the plurality of bit lines and a corresponding one of the plurality of word line contacts, which is adjacent to the one of the plurality of bit lines in the first horizontal direction. ([0046], the memory cell 300 is surrounded by an insulator material to provide electrical isolation.)
Regarding claim 19, Gomes further discloses :
wherein the upper electrode film (Fig. 3,electrode 328) covers the capacitor dielectric film covering the plurality of lower electrode layers (electrode 386) and has a plate shape portion extending in the second horizontal direction and the vertical direction. (Fig. 2, capacitor plateline PL, which would have a shape in both the horizontal and vertical direction in the array.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Gomes US 20210159229 A1 (hereinafter Gomes) in view Li US 20240023310 A1 (hereinafter Li).
Regarding claim 1, Gomes discloses:
A semiconductor memory device (Fig. 2-4B memory device with 1T-1C using a nanoribbon-based field effect transistor FET) comprising:
a semiconductor layer comprising a source area (Fig. 3, second S/D region314-2), a channel area (nanoribbon 304, [0049] the channel material of the nanoribbon.), and a drain area (first source 3/D region 314-1) arranged in a first horizontal direction on a substrate; (Fig. 3, base 302)
a cell capacitor (Fig. 2, capacitor 220 and Fig. 3, capacitor 320) extending in the first horizontal direction on the substrate and comprising a lower electrode layer (Fig. 3, electrode 326), a capacitor dielectric film (capacitor dielectric 330), and an upper electrode layer (electrode 328) connected to the source area; (Fig. 4A, [0066], a second S/D region coupled to a capacitor 420-12)
a bit line (Fig. 2 bit line BL 240 and Fig. 4A, bit line BL 440) extending in a vertical direction on the substrate and connected to the drain area; and (Fig. 4A, [0066] a first S/D region coupled to the BL 440)
a gate structure (Fig. 2, gate 210 and Fig. 3, gate stack 306 which includes gate electrode 308 and gate dielectric 312) covering the channel area (nanoribbon 304), the gate structure comprising a gate dielectric film (gate dielectric 312) on the channel area and a gate electrode film (gate electrode 308) on the gate dielectric film, (gate dielectric 312)
Gomes does not appear to disclose:
wherein in the vertical direction, a first thickness of an end of the channel area facing the source area is greater than a second thickness of another end of the channel area facing the drain area.
Li, which teaches a semiconductor memory device including a channel with regions with one areas being smaller than another (Li, Abstract), discloses:
wherein in the vertical direction, a first thickness of an end of the channel area (Fig. 1, channel region 205) facing the source area (Fig 1, source region 207) is greater than a second thickness of another end of the channel area facing the drain area. (Fig. 1, drain region 206. [0031], the size of the channel 205 gradually increases linearly from the drain region 206 to the source region 207.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gomes to have in the vertical direction, a first thickness of an end of the channel area facing the source area is greater than a second thickness of another end of the channel area facing the drain area as taught by Li for purposes of avoid the leakage current in the off state in a junctionless field-effect transistor. (Li, [0018]-[0019].)
Regarding claim 2, Gomes and Li disclose all the elements of claim 1.
Li further discloses:
wherein a thickness of the channel area decreases from the source area toward the drain area. (Li, Fig. 1, [0031], the size of the channel 205 gradually decreases linearly from the source region 207 towards the drain region 206.)
Regarding claim 3, Gomes and Li disclose all the elements of claim 1.
Li further discloses:
wherein a thickness of the source area in the vertical direction is the first thickness. (Fig. 1, [0034], the source region 207 has a first thickness of 15 nm to 50 nm.)
Regarding claim 4, Gomes and Li disclose all the elements of claim 1.
Li further discloses:
wherein a thickness of the drain area in the vertical direction is less than or equal to the second thickness. (Fig. 1, the drain region 206 has thickness in the vertical direction which is between about 4-20.)
Regarding claim 5, Gomes and Li disclose all the elements of claim 1.
Gomes further discloses:
a word line contact (Fig. 4A, gate contact 452-11) connected to the gate structure ([0066], the gate stack 306 is connected to the gate contact 452-11) and extending in the vertical direction. (See Fig. 4A)
Regarding claim 6, Gomes and Li disclose all the elements of claim 5.
Gomes further discloses:
wherein a bottom surface of the word line contact contacts a portion of the gate electrode film covering a top surface of the channel area. (See Fig. 4A, the bottom of gate contact 452-11 is cover the top surface of the gate stack 306.)
Regarding claim 7, Gomes and Li disclose all the elements of claim 1.
Gomes further discloses:
wherein the semiconductor layer (See Fig. 3, S/D regions 314-1 and 314-2 and nanoribbon 304) and the cell capacitor (capacitor 320) are arranged in the first horizontal direction, (See Fig. 3, S/D regions 314-1 and 314-2 and nanoribbon 304 is arranged with capacitor 320) and the semiconductor layer and the gate structure constitute a cell transistor. (See Fig. 3, access transistor 310 comprises S/D regions 314-1 and 314-2 and nanoribbon 304.)
Regarding claim 8, Gomes and Li disclose all the elements of claim 1.
Gomes further discloses:
wherein the cell transistor comprises a plurality of cell transistors apart from one another in a second horizontal direction orthogonal to the first horizontal direction and in the vertical direction, (See Fig. 4B and [0067] the access transistors of the memory cells 400-11, 400-21, 400-31, and 400-41 may be stacked over one another.) and the plurality of cell transistors are arranged in columns and rows. (By necessity the cell transistors are arranged in columns and rows.)
Regarding claim 9, Gomes and Li disclose all the elements of claim 8.
While Gomes teaches where the 3D DRAM can be used in memory which has a density of memory cells in an array [0019], therefore Gomes discloses “the bit line comprises a plurality of bit lines arranged apart from one another in the second horizontal direction.”
Gomes, Fig. 2, further shows, “a respective one of the plurality of bit lines is connected to the drain areas of a first group of cell transistors,” due to the drain of the access transistor 210 being connected to the bit line 240 and world line 250 as part of the memory cell 200. Fig. 4A shows that that “the drain areas of the first group of cell transistors” would by necessity be “arranged apart from one another in the vertical direction.”
Regarding claim 10, Gomes and Li disclose all the elements of claim 8.
While Gomes teaches where the 3D DRAM can be used in memory which has a density of memory cells in an array [0019], therefore Gomes discloses “the gate structure comprises a plurality of gate structures.” Fig. 4B shows the gate stack 406-11 which is “arranged apart from one another in the vertical direction.” By necessity as each gate stack 406-11 would by necessity of repeating the memory cell structure mean that Gomes also shows “the plurality of gate structures each cover the channel area of a corresponding one of a second group of cell transistors” and “the second group of cell transistors arranged apart from one another in the second horizontal direction and extend in the second horizontal direction” as shown by Fig. 4B.
Regarding claim 11, Gomes disclose:
A semiconductor memory device (Fig. 2-4B memory device with 1T-1C using a nanoribbon-based field effect transistor FET) comprising:
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array) semiconductor layer comprising a source area (Fig. 3, second S/D region314-2), a channel area (nanoribbon 304, [0049] the channel material of the nanoribbon.), and a drain area (first source 3/D region 314-1) arranged in a first horizontal direction on a substrate; (Fig. 3, base 302 ) the plurality of semiconductor layers being apart from one another in a second horizontal direction orthogonal to the first horizontal direction and in a vertical direction, (Fig. 4A and 4B show that the layers are further connected with would have semiconductor layers spaced apart in a second horizontal direction and in a vertical direction.) the plurality of semiconductor layers arranged in columns and rows; (an array by necessity is arranged in columns and rows which would have layers.)
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array.) of cell capacitors (Fig. 2, capacitor 220 and Fig. 3, capacitor 320) extending in the first horizontal direction from the plurality of semiconductor layers, (See Fig. 4B) the plurality of cell capacitors comprising a plurality of lower electrode layers (Fig. 3, electrode 326) connected to source areas of the plurality of semiconductor layers, (Fig. 4A, [0066], a second S/D region coupled to a capacitor 420-12) a capacitor electrode dielectric film (capacitor dielectric 330) covering the plurality of lower electrode layers, (electrode 328) and an upper electrode film covering the capacitor electrode dielectric film; (See Fig. 4A.)
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array.) of bit lines (Fig. 2 bit line BL 240 and Fig. 4A, bit line BL 440) extending in the vertical direction on the substrate, the plurality of bit lines arranged apart from one another in the second horizontal direction, (See Fig. 4B) the plurality of bit lines each connected to the drain area of a corresponding one of the plurality of semiconductor layers; and (Fig. 4A, [0066] a first S/D region coupled to the BL 440)
a plurality ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array.) of gate structures (Fig. 2, gate 210 and Fig. 3, gate stack 306 which includes gate electrode 308 and gate dielectric 312) covering the channel areas (nanoribbon 304) of the plurality of semiconductor layers and extending in the second horizontal direction, (See Fig. 4A) the plurality of gate structures each comprising a gate dielectric film (gate dielectric 312) on the channel area and a gate electrode film on the gate dielectric film, (See Fig.3)
Gomes does not appear to disclose:
wherein a thickness of the channel area in the vertical direction decreases from the source area toward the drain area.
Li, which teaches a semiconductor memory device including a channel with regions with one areas being smaller than another (Li, Abstract), discloses:
wherein a thickness of the channel area in the vertical direction decreases from the source area toward the drain area. (Fig. 1, drain region 206. [0031], the size of the channel 205 gradually increases linearly from the drain region 206 to the source region 207.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gomes to have a thickness of the channel area in the vertical direction decreases from the source area toward the drain area as taught by Li for purposes of avoid the leakage current in the off state in a junctionless field-effect transistor. (Li, [0018]-[0019].)
Regarding claim 12, Gomes and Li disclose all the elements of claim 11.
a plurality of word line contacts extending in the vertical direction, (See Fig. 4A, gate contacts 452-11, 452-21, 452-31, 452-41) the plurality of word line contacts connected to the plurality of gate structures (See Fig. 4B, gate stack406-11 connects with 452-11. Similarly while not labeled a respective gate stack connects with gate contact 452-21, 452-31 and 452-41) and arranged apart from one another in the second horizontal direction. (See Fig. 4A and 4B.)
Regarding claim 13, Gomes and Li disclose all the elements of claim 12.
Gomes further disclose:
wherein the plurality of word line contacts (gate structures 452-11, 452-21, 452-31, 452-41) are connected to a group of gate structures (gate stack 406-11 and the related gate stacks below), from among the plurality of gate structures, located at different vertical levels, respectively. (See Fig. 4A, the gate structures are located at different vertical levels.)
Regarding claim 14, Gomes and Li disclose all the elements of claim 13.
Gomes further discloses:
wherein the plurality of word line contacts (gate structures 452-11, 452-21, 452-31, 452-41) have different extension lengths in the vertical direction. (See Fig. 4A, the gate structures are located at different vertical levels.)
Regarding claim 15, Gomes and Li disclose all the elements of claim 12.
Gomes further discloses:
wherein each of the plurality of gate structures surrounds the channel area by covering a top surface and a bottom surface of the channel area of a corresponding one of the plurality of semiconductor layers and two side surfaces of the channel area of the corresponding one of the plurality of semiconductor layers connecting the top surface and the bottom surface. (See Fig. 3, gate material 308 surrounds the nanoribbon 304.)
Regarding claim 16, Gomes and Li disclose all the elements of claim 15.
Gomes further discloses:
wherein a bottom surface of each of the plurality of word line contacts contacts a portion of the gate electrode film covering a top surface of the channel area of a corresponding one of the plurality of semiconductor layers. (See Fig. 4A, the bottom of gate contact 452-11 is covering the top surface of the gate stack 306.)
Regarding claim 17, Gomes and Li disclose all the elements of claim 11.
Gomes further disclose:
wherein one of the plurality of semiconductor layers (See Fig. 3, S/D regions 314-1 and 314-2 and nanoribbon 304) and a corresponding one of the plurality of cell capacitors (capacitor 320) are arranged in the first horizontal direction, (See Fig. 3, S/D regions 314-1 and 314-2 and nanoribbon 304 is arranged with capacitor 320) the plurality of semiconductor layers constitute a plurality of cell transistors with corresponding ones of the plurality of gate structures, (See Fig. 3, access transistor 310 comprises S/D regions 314-1 and 314-2 and nanoribbon 304.) and the plurality of cell transistors are arranged to be mirror symmetric in the first horizontal direction. ([0019], the 1T-1C memory is implement in 3D RAM in having a density of memory cells in an memory array and would by necessity have mirror symmetry as a result of the manufacturing of the array.)
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Gomes as applied to claim 18 above, and further in view of Li.
Regarding claim 20, Gomes discloses all the elements of claim 18.
Gomes does appear to disclose:
wherein in the vertical direction,
a first thickness of an end of the channel area facing the source area is from 20 nm to 50 nm, and
a second thickness of another end of the channel area facing the drain area is less than the first thickness and is from 5 nm to 20 nm.
Li, which teaches a semiconductor memory device including a channel with regions with one areas being smaller than another (Li, Abstract), discloses:
a first thickness of an end of the channel area facing the source area is from 20 nm to 50 nm, and (Fig. 1, [0034] the first thickness being equal the thickness of the channel area being next to the source region and the source region being about 15-50 nm.)
a second thickness of another end of the channel area facing the drain area is less than the first thickness and is from 5 nm to 20 nm. (Fig. 1, [0034] the second thickness being equal to the thickness of the channel area next to drain region and the drain region being about 4-20 nm.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gomes to have a first thickness of an end of the channel area facing the source area is from 20 nm to 50 nm, and a second thickness of another end of the channel area facing the drain area is less than the first thickness and is from 5 nm to 20 nm as taught by Li for purposes of avoid the leakage current in the off state in a junctionless field-effect transistor. (Li, [0018]-[0019].)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Machkaoutsan et al. US 20200212041 A1 – 3D DRAM using a 1T-1C array in Fig. 1 and Fig. 40 showing a single-gated transistor formed in the memory cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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