DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to KR10-2023-0075442 for 06/13/2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/12/2023 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR MEMORY DEVICE HAVING AN INVERTED SELECTION GATE LINE STRUCTURE AND METHOD OF MANUFACTURING THEREOF
Claim Objections
Claims 1, 3, and 15 are objected to because of the following informalities:
Claim 1, line 2 should read: “
Claim 1, line 4 should read: “
Claim 3, line 3 should read: “
Claim 15 makes reference to “between the channel structures,” plural, which have previously only been described as “a channel structure,” singular, in claim 14. Examiner recommends that claim 14 is amended to read “further comprising <a> channel structures that extends through”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 9, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US PGPub 2021/0313343; herein known as Jung) in view of Lee et al. (US PGPub 2022/0077182).
Regarding claim 1, Jung teaches (Figs. 5A-5E) a semiconductor memory device comprising: a first gate structures (LST2, [0068]) each comprising interleaved first real gate lines (SSLa2, SSLb2, [0069]) and first insulating layers (91A2, [0069]); a first dummy gate lines (DWL, [0076]) located on the first gate structures, respectively; a separation insulating structure (55, [0068]) formed within and configured to extend between the first dummy gate lines and between the first gate structures ([0068]); and a second gate structure (UST, [0070]) located on the first gate structures (LST2) and the separation insulating structure (55), the second gate structure comprising a second dummy gate line (DDSLa, [0076]).
Jung does not explicitly teach a second dummy gate line having greater width than each of the first dummy gate lines.
Lee teaches wherein gate line width increases in a vertical direction, thus second gate lines (23/WL) having greater width than each of the first gate lines (23/23A).
Because Jung and Lee are both directed toward memory gate stacks, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung and Lee to include a second dummy gate line having greater width than each of the first dummy gate lines in order to allow for an improved alignment margin of the source isolation insulating layer (Lee, [0050]).
Regarding claim 2, Jung in view of Lee teaches (Jung, Fig. 2, Fig. 5D) the semiconductor memory device of claim 1, wherein the first dummy gate lines (DWL, [0076]) and the second dummy gate lines (DDSLa, [0076]) are electrically connected to each other (connected via the channel layers, [0041]).
Regarding claim 3, Jung in view of Lee teaches (Jung, Figs. 5A-5E) the semiconductor memory device of claim 1, wherein the second gate structure (UST, [0070]) comprises: a second real gate lines (WL, [0070]) stacked on the second dummy gate line; and second insulating layers (93A, [0070]), alternately stacked on the second dummy gate line along with the second real gate lines ([0070]).
Regarding claim 4, Jung in view of Lee teaches (Jung, Figs. 5A-5E) the semiconductor memory device of claim 3, wherein: the first real gate lines (SSLB2, SSLb2, [0069]) are selection lines ([0069]), and the second real gate lines (WL, [0070]) are word lines ([0070]).
Regarding claim 5, Jung in view of Lee teaches the semiconductor memory device of claim 3, wherein the second gate structure has a width greater than a width of the first gate structures (Lee, [0050]).
Regarding claim 8, Jung in view of Lee teaches (Jung, annotated Fig. 5C below) the semiconductor memory device of claim 1, wherein the separation insulating structure (55, [0068]) comprises: a first part having a first width (Wf), and a second part having a second width (Wi, [0079]) greater than the first width (Wi > Wf).
PNG
media_image1.png
585
424
media_image1.png
Greyscale
Regarding claim 9, Jung in view of Lee teaches (Jung, annotated Fig. 5C above) the semiconductor memory device of claim 8, wherein the second part (Wi, [0079]) is closer to the second gate structure (UST, [0069]) than is the first part (Wf).
Regarding claim 14, Jung in view of Lee teaches (Jung, Figs. 5A-5E) the semiconductor memory device of claim 1, further comprising a channel structure (CH1, [0071]) that extends through the second gate structure (UST, [0071]), the first dummy gate lines (DWL, [0076]), and the first gate structures (LST2, [0071]).
Regarding claim 15, Jung in view of Lee teaches (Jung, Figs. 5A-5E) the semiconductor memory device of claim 14, wherein the separation insulating structure (55, [0069]) is located between the channel structures (CH1, CH2, [0071]).
Claims 6, 7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Lee as applied to claim 1 above, and further in view of Sim et al. (US PGPub 2023/0247835; herein known as Sim).
Regarding claim 6, Jung in view of Lee teaches the semiconductor memory device of claim 3, but does not explicitly teach wherein the separation insulating structure extends into a lowermost second insulating layer, among the second insulating layers.
Sim teaches (Fig. 9A) wherein the separation insulating structure (BS2, [0123]) extends into a lowermost second insulating layer (12, [0122]) among the second insulating layers ([0122]).
Because Jung in view of Lee and Sim are directed toward memory stack devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung in view of Lee and of Sim to include wherein the separation insulating structure extends into a lowermost second insulating layer, among the second insulating layers in order to allow for polishing and formation of a flat separation pattern (Sim, [0124]).
Regarding claim 7, Jung in view of Lee and Sim teaches (Sim, Fig. 5A) the semiconductor memory device of claim 6, wherein an upper surface of the separation insulating structure (BS1, [0124]) is located between an upper surface and lower surface of the lowermost second insulating layer (12, 14a, shown in figure).
Regarding claim 13, Jung in view of Lee teaches the semiconductor memory device of claim 1, having a lowermost second insulating layer among the second insulating layers, but not wherein it comprises a sacrificial layer and an insulating layer located on the sacrificial layer, and the separation insulating structure contacts a lower surface of the insulating layer through the sacrificial layer.
Sim teaches (Fig. 5A) wherein it comprises a sacrificial layer (14b1, [0122]) and an insulating layer (12, [0122]) located on the sacrificial layer, and the separation insulating structure (BS1, [0123]) contacts a lower surface of the insulating layer through the sacrificial layer.
Because Jung in view of Lee and Sim are directed toward memory stack devices, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung in view of Lee and of Sim to include wherein it comprises a sacrificial layer and an insulating layer located on the sacrificial layer, and the separation insulating structure contacts a lower surface of the insulating layer through the sacrificial layer in order to allow for polishing and formation of a flat separation pattern (Sim, [0124]).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Lee as applied to claim 1 above, and further in view of Son et al. (US PGPub 2022/0310652; herein known as Son) and Kim et al. (2018/0190668; herein known as Kim).
Regarding claim 10, Jung in view of Lee teaches the semiconductor memory device of claim 1, but does not explicitly teach wherein: the first insulating layers each have a first thickness, and the first real gate lines each have a second thickness greater than the first thickness.
Son teaches (Fig. 3) wherein the first insulating layers (110a, [0029]) each have a first thickness, and the first real gate lines (EGE, GGE, [0029]) each have a second thickness (shown in Fig. 3) greater than the first thickness (see Fig. 3, thickness of 110a less than thickness of gate lines EGE and GGE).
Kim teaches wherein the thickness of the insulating layer between gate layers can be modified according to device requirements, and wherein reducing the thickness of the insulating layers positioned between gate layers beneficially reduces the overall height of a memory device.
Absent a teaching of criticality of the claimed relationship of thicknesses between the insulating layers and gate lines, it would have been obvious to one of ordinary skill in the art before the filing date of the claimed invention to combine the teachings of Jung in view of Lee, Son, and Kim to include wherein: the first insulating layers each have a first thickness, and the first real gate lines each have a second thickness greater than the first thickness, as this would constitute a result effective variable impacting the height of the resulting memory device. See MPEP 2144.05(II)(C).
Regarding claim 11, Jung in view of Lee, Son, and Kim teaches (Jung, Figs. 5A-5E) the semiconductor memory device of claim 10, wherein the first dummy gate lines (Jung, DWL, [0049]) each have a third thickness substantially identical with the second thickness (Jung, [0049], disclosed to be deposited at same levels).
Regarding claim 12, Jung in view of Lee, Son, and Kim teaches (Son, Fig. 3) the semiconductor memory device of claim 10, wherein a lowermost second insulating layer (50, [0029]), among the second insulating layers (110b, [0029]), has a fourth thickness greater than the first thickness (see Fig. 3, thickness of 50 greater than the thickness of 110b, [0029]).
REASONS FOR ALLOWANCE
Claims 16-32 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 16, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a method of manufacturing a semiconductor device, comprising: forming a second sacrificial layer on top of the first stack; forming a preliminary insulating structure within the opening; forming a separation insulating structure within the opening by etching the preliminary insulating structure and the second sacrificial layer so that the first sacrificial layer is exposed.
Sim teaches (Figs. 7A-13A) a method of manufacturing a semiconductor device, comprising forming a first stack comprising first material layers and second material layers that are alternately stacked; forming a first sacrificial layer on top of the first stack, forming an opening that extends through the first sacrificial layer and into the first stack, and forming, on the separation insulating structure and the first sacrificial layer, a second stack comprising third material layers and fourth material layers that are alternately stacked. Sim does not teach not suggest forming a second sacrificial layer on top of the first stack and first sacrificial layer, which would add additional process steps to the method and would not be obvious to one of ordinary skill in the art to include as an added step. Additionally, Sim does not teach nor suggest etching the preliminary insulating structure, and it would not have been obvious to one of ordinary skill to complete this step, as it could result in damage to the etched layers.
Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Claims 17-32 are allowed as dependent on claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812