DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lowes et al. (CN 104737313 A) in view of Tanabiki (US 2022/0301983 A1).
In regard to claim 1, Lowes (paragraphs 200, 201, Figs. 4-9, 20-35, 39, 41, 57-64, 90-97 and associated text and items) discloses a semiconductor device comprising: a substrate (item 54 plus 60a plus 60b plus 154a plus 154b); and a semiconductor element (items 152a, 152b), wherein the substrate (item 54 plus 60a plus 60b plus 154a plus 154b) includes a base (item 54) and a conductor pattern (items 154a, 154b, U-shaped, paragraphs 200, 202, 222) arranged on the base (item 54), wherein the conductor pattern (items 154a, 154b, U-shaped, paragraphs 200, 202, 222) includes a die pad portion (where items 152a or 152b reside on items 154a or 54b), a first connection portion (end of one leg of U-shaped item 154a or 154b), and a second connection portion (end of another leg of U-shaped item 154a or 154b), wherein the die pad portion (where items 152a or 152b reside on items 154a or 54b) includes a first end and a second end which are both ends in a first direction in a plan view, and a third end and a fourth end which are both ends in a second direction orthogonal to the first direction in the plan view, wherein an outer periphery of the die pad portion (where items 152a or 152b reside on items 154a or 54b) includes a first side and a second side extending in the second direction in the plan view, and a third side and a fourth side extending in the first direction in the plan view, wherein the first side and the second side constitute the first end and the second end, respectively, wherein the third side and the fourth side constitute the third end and the fourth end, respectively, wherein a recess (recess shown from U-shaped items 154a or 154b) is formed on one of the first side and the second side so as to be recessed toward the other of the first side and the second side, wherein the first connection portion (end of one leg of U-shaped item 154a or 154b), and the second connection portion (end of another leg of U-shaped item 154a or 154b) are respectively connected to a first corner of the outer periphery of the die pad portion (where items 152a or 152b reside on items 154a or 54b) where the second side and the third side are joined, and a second corner of the outer periphery of the die pad portion (where items 152a or 152b reside on items 154a or 54b) where the second side and the fourth side are joined. Examiner notes that Lowes discloses that the conductor pattern can have various shapes (paragraphs 200, 201).
It would have been obvious to modify the invention to include U-shaped conductor pattern, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Lowes does not specifically disclose wherein the semiconductor element is arranged on the die pad portion so as to be located between the first side or the second side and a bottom of the recess in the plan view.
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Fig. 1, Tanabiki
Tanabiki (Fig. 1 and associated text) discloses a die pad portion (where item 30 resides on item 20), a first connection portion (item 11), and a second connection portion (item 11), wherein the die pad portion (where item 30 resides on item 20) includes a first end and a second end which are both ends in a first direction in a plan view, and a third end and a fourth end which are both ends in a second direction orthogonal to the first direction in the plan view, wherein an outer periphery of the die pad portion (where item 30 resides on item 20) includes a first side and a second side extending in the second direction in the plan view, and a third side and a fourth side extending in the first direction in the plan view, wherein the first side and the second side constitute the first end and the second end, respectively, wherein the third side and the fourth side constitute the third end and the fourth end, respectively, wherein a recess (recess shown by way of items 11 and 23) is formed on one of the first side and the second side so as to be recessed toward the other of the first side and the second side, wherein the first connection portion (item 11), and the second connection portion (item 11) are respectively connected to a first corner of the outer periphery of the die pad portion (where item 30 resides on item 20) where the second side and the third side are joined, and a second corner of the outer periphery of the die pad portion (where item 30 resides on item 20) where the second side and the fourth side are joined, and wherein the semiconductor element (item 30) is arranged on the die pad portion (where item 30 resides on item 20) so as to be located between the first side or the second side and a bottom of the recess (recess shown by way of items 11 and 23) in the plan view.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings Tanabiki for the purpose of an electrical and mechanical connection, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
In regard to claim 2, Lowes (paragraphs 200, 201, Figs. 4-9, 20-35, 39, 41, 57-64, 90-97 and associated text and items) alone, or as modified by Tanabiki (Fig. 1 and associated text) discloses wherein the recess (recess shown from U-shaped items 154a or 154b, Lowes, recess shown by way of items 11 and 23, Lowes) is formed on the second side.
In regard to claim 3, Lowes (paragraphs 200, 201, Figs. 4-9, 20-35, 39, 41, 57-64, 90-97 and associated text and items) as modified by Tanabiki (Fig. 1 and associated text) does not specifically disclose wherein a value obtained by subtracting a width of the semiconductor element (items 152a, 152b, Lowes, item 30, Tanabiki) in the first direction from a distance between the first side or the second side and the bottom of the recess (recess shown from U-shaped items 154a or 154b, Lowes, recess shown by way of items 11 and 23, Lowes) in the first direction is 0.05 mm or more and 0.40 mm or less.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a value obtained by subtracting a width of the semiconductor element in the first direction from a distance between the first side or the second side and the bottom of the recess in the first direction being 0.05 mm or more and 0.40 mm or less., since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
Examiner note that the Applicant has not given any criticality to where this yields an advantage or unexpected result other the prevent misalignment and suppressing a short circuit, which one of ordinary skill in the art would be aware and take into consideration.
In regard to claim 4, Lowes (paragraphs 200, 201, Figs. 4-9, 20-35, 39, 41, 57-64, 90-97 and associated text and items) alone, or as modified by Tanabiki (Fig. 1 and associated text) discloses wherein the recess (recess shown from U-shaped items 154a or 154b, Lowes, recess shown by way of items 11 and 23, Lowes) is rectangular, triangular, or partially circular in the plan view.
In regard to claim 5, Lowes (Figs. 4-9, 20-35, 39, 41, 57-64, 90-97 and associated text and items) discloses wherein the semiconductor element (items 152a, 152b) is an LED (paragraph 221).
In regard to claim 7, Lowes (paragraphs 200, 201, Figs. 4-9, 20-35, 39, 41, 57-64, 90-97 and associated text and items) discloses a method of manufacturing a semiconductor device, comprising: preparing a substrate (item 54 plus 60a plus 60b plus 154a plus 154b) including a base (item 54) and a conductor layer (item 60a plus 60b plus 154a plus 154b) arranged on the base (item 54); forming a conductor pattern (items 154a, 154b) including a die pad portion (where items 152a, 152b reside) by patterning the conductor layer (item 60a plus 60b plus 154a plus 154b); and mounting a semiconductor element (items 152a, 152b) on the die pad portion (where items 152a, 152b reside), wherein the die pad portion (where items 152a, 152b reside) includes a first end and a second end which are both ends in a first direction in a plan view, wherein an outer periphery of the die pad portion (where items 152a, 152b reside) includes a first side extending in a second direction orthogonal to the first direction in the plan view to constitute the first end, and a second side extending in the second direction to constitute the second end, wherein when forming the die pad portion (where items 152a, 152b reside) by patterning the conductor layer (item 60a plus 60b plus 154a plus 154b), a recess (recess shown from U-shaped items 154a or 154b) is formed on one of the first side and the second side so as to be recessed toward the other of the first side and the second side, but does not specifically disclose and wherein the semiconductor element is arranged so as to be located between the first side or the second side and a bottom of the recess in the plan view.
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Fig. 1, Tanabiki
Tanabiki (Fig. 1 and associated text) discloses wherein the semiconductor element (item 30) is arranged on the die pad portion (where item 30 resides on item 20) so as to be located between the first side or the second side and a bottom of the recess (recess shown by way of items 11 and 23) in the plan view.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings Tanabiki for the purpose of an electrical and mechanical connection, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lowes et al. (CN 104737313 A) in view of Tanabiki (US 2022/0301983 A1) as applied to claims 1-5 and 7 above, and further in view of Inoue et al. (Inoue) (US 2015/0207014 A1).
In regard to claim 6, Lowes (paragraphs 200, 201, Figs. 4-9, 20-35, 39, 41, 57-64, 90-97 and associated text and items) as modified by Tanabiki (Fig. 1 and associated text) discloses the semiconductor device of claim 5, but does not specifically disclose a sensor comprising: the semiconductor device of claim 5; and a light-receiving element, wherein the light-receiving element is arranged to receive light from the LED.
Inoue (Figs. 8-10, 12 and associated text) discloses a sensor (item 4) comprising: a semiconductor device (item 45); and a light-receiving element (items E1 or E1 plus IRcutF), wherein the light-receiving element (items E1 or E1 plus IRcutF) is arranged to receive light from the LED (item 45, paragraph 271).
Therefore it would have been obvious to one o ordinary skill in the art before the effective filing date to incorporate the teachings of Inoue for the purpose of an illuminance/proximity sensor (Abstract, paragraph 33).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 December 9, 2025