DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/12/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-10, 14, 16 and 19 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tsai et. al. (US-2021/0057298-A1, hereinafter Tsai),
Regarding Claim 1.
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Tsai teaches in Fig. 3A and in related text A semiconductor device, comprising:
a chip carrier (#C);
a semiconductor chip (#200) arranged on the chip carrier;
an intermediate layer (#100) arranged between the chip carrier and the semiconductor chip;
an encapsulation material (#300) at least partially encapsulating the semiconductor chip; and
filler particles (#320) embedded in at least one of the intermediate layer or the encapsulation material,
wherein the filler particles comprise a semiconductor material with a band gap in a range from 2.3 eV to 3.6 eV.([0018] the filler particles #320 comprise Zinc Oxide. It is well established in the art that Zinc Oxide is a semiconductor material having a band gap within the claimed range of 2.3-3.6 eV)
Regarding Claim 2.
Tsai teaches A semiconductor device as claimed in claim 1,
Tsai further teaches wherein the filler particles comprise at least one of zinc oxide or silicon carbide. .([0018] the filler particles #320 comprise Zinc Oxide.)
Regarding Claim 5.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai further teaches wherein a proportion of the filler particles in at least one of the intermediate layer or the encapsulation material has a value in a range from 1 percent by weight to 99 percent by weight.([0018])
Regarding Claim 6.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai further teaches wherein the filler particles have maximum dimensions in a range from 1 μm to 300 μm. ([0018])
Regarding Claim 7-10.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai further teaches in Fig.3A
(claim 7) wherein the filler particles are arranged in a region in which an electric field strength is increased due to a geometric shape of at least one of the semiconductor chip, the intermediate layer, the chip carrier, or the encapsulation material. (Fig.3A geometric enhancement at chip corners region R)
(claim 8) wherein the filler particles are arranged at least at one of an edge of the semiconductor chip or a tip of the semiconductor chip.
(claim 9) wherein the filler particles are arranged in a region in which the semiconductor chip, the encapsulation material, and the intermediate layer are adjacent to one another.
(claim 10) wherein the filler particles are distributed homogeneously and completely over an entire portion of encapsulation material.
(See Tsai Fig.3A [0017-0020])
Regarding Claim 14.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai further teaches wherein the encapsulation material comprises at least one of a molding compound, an epoxy, an imide, a thermoplastic, a thermoset polymer, a polymer mixture, a glob-top material or a laminate. ([0018] In some embodiments, the material of the base material 310 includes epoxy resins, phenolic resins or silicon-containing resins, or the like)
Regarding Claim 16.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai further teaches in Fig.6A wherein the semiconductor chip is part of a gate driver.([0044])
Regarding Claim 19.
Tsai further teaches A method for producing a semiconductor device, the method comprising:
arranging an intermediate layer (#100) on a chip carrier;
arranging a semiconductor chip (#200) on the intermediate layer; and
encapsulating the semiconductor chip with an encapsulation material (#300),
wherein filler particles are embedded in at least one of the intermediate layer or the encapsulation material, which comprise a semiconductor material with a band gap in a range from 2.3 eV to 3.6 eV. ([0018] the filler particles #320 comprise Zinc Oxide. It is well established in the art that Zinc Oxide is a semiconductor material having a band gap within the claimed range of 2.3-3.6 eV)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US-2021/0057298-A1, hereinafter Tsai), and further in view of Brunschwiler et. al. (US-2013/0062789-A1, hereinafter Brunschwiler).
Regarding Claim 11.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai does not explicitly disclose wherein the filler particles are distributed homogeneously and completely over an entire portion of intermediate layer.
However, Brunschwiler teaches in Fig.2 and in related text wherein the filler particles (#9) are distributed homogeneously and completely over an entire portion of intermediate layer (#4).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Tsai’s semiconductor device with the teachings of Brunschwiler, as identified above, as homogeneous distribution of filler particles is a well-recognized manufacturing objective in filled polymer systems, as it ensures consistent material properties throughout the layer.
Regarding Claim 12.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai does not explicitly disclose wherein:
the intermediate layer comprises a dielectric layer, which is configured to provide galvanic isolation between the chip carrier and the semiconductor chip, and
the filler particles are embedded in the dielectric layer.
However, Brunschwiler teaches the intermediate layer (#4) comprises a dielectric layer (#10), which is configured to provide galvanic isolation between the chip carrier (37) and the semiconductor chip (#8), and the filler particles (#9) are embedded in the dielectric layer (#10).
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Tsai’s semiconductor device with the teachings of Brunschwiler, as identified above, as dielectric layer with embedded filler particles is a well-recognized manufacturing objective in filled polymer systems, as it ensures consistent material properties throughout the layer. The combination represents a straightforward application of known techniques to achieve predictable result.
Regarding Claim 13.
Tsai teaches The semiconductor device as claimed in claim 1,
Brunschwiler teaches wherein:
the intermediate layer comprises an adhesive layer, which is configured to fix the semiconductor chip to the chip carrier, and the filler particles (#9) are embedded in the adhesive layer.([0064])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Tsai’s semiconductor device with the teachings of Brunschwiler, as identified above, as die-attaching adhesive layer are one of the most ubiquitous intermediate layers in semiconductor packaging. The combination represents a straightforward application of known techniques to achieve predictable result.
Claims 3-4, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US-2021/0057298-A1, hereinafter Tsai), and further in view of Onneby et, al, (US-US-2006/0145119-A1)
Regarding Claim 3.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai does not explicitly disclose wherein the filler particles are configured to increase at least one of an electrical conductivity of the intermediate layer or an electrical conductivity of the encapsulation material into a range from 10−16 S/m to 10−2 S/m upon an increase in an electric field strength to a value of more than 5 V/μm.
However, Onneby teaches the ZnO and SiC, identified as the preferred semiconducting filler materials, inherently produce nonlinear, field-dependent conductivity in polymer composites. And the onset of the nonlinear resistance is explicitly described as tunable through particle size selection and is shown in Fig.5 to increase with decreasing particle size, providing the skilled artisan with clear design guidance for achieving a threshold in the range around 5 V/um. And resistivity vs filler concentration data (Fig.2) demonstrate conductivity behavior spanning the broadly claimed 10−16 S/m to 10−2 S/m range. These limitations would have been obvious to one of ordinary skill in the art at the time of the invention because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range.
Regarding Claim 4.
Tsai modified by Onneby teaches The semiconductor device as claimed in claim 3, Onneby further disclose wherein the increase in the electrical conductivity is configured to reduce the electric field strength at positions of the filler particles.
This limitation recites only the physically inevitable and directly documented consequence of the conductivity increase already established in Claim 3, and does not introduce any additional patentable distinction. This result is physically inevitable from the governing electromagnetic constitutive relation where in a dielectric medium containing locally conductive filler particles, when the conductivity at a filler particle position increases in response to an elevated electric field, the local field at that same position necessarily decreases for a given current density. Accordingly, claim 4 recites only the inherent physical consequence of the prior art combination, no inventive step is present.
Regarding Claim 17.
Tsai teaches A semiconductor device, comprising:
a chip carrier (#C);
a semiconductor chip (#200) arranged on the chip carrier;
an intermediate layer (#100) arranged between the chip carrier and the semiconductor chip;
an encapsulation material (#300) at least partially encapsulating the semiconductor chip; and
filler particles (#320) embedded in at least one of the intermediate layer or the encapsulation material,
Tsai does not explicitly disclose which are configured to increase at least one of an electrical conductivity of the intermediate layer or an electrical conductivity of the encapsulation material into a range from 10−16 S/m to 10−2 S/m upon an increase in an electric field strength to a value of more than 5 V/μm.
However, Onneby teaches the ZnO and SiC, identified as the preferred semiconducting filler materials, inherently produce nonlinear, field-dependent conductivity in polymer composites. And the onset of the nonlinear resistance is explicitly described as tunable through particle size selection and is shown in Fig.5 to increase with decreasing particle size, providing the skilled artisan with clear design guidance for achieving a threshold in the range around 5 V/um. And resistivity vs filler concentration data (Fig.2) demonstrate conductivity behavior spanning the broadly claimed 10−16 S/m to 10−2 S/m range. These limitations would have been obvious to one of ordinary skill in the art at the time of the invention because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range.
Regarding Claim 18.
Tsai modified by Onneby teaches The semiconductor device as claimed in claim 17, Tsai further teaches wherein the filler particles comprise a semiconductor material with a band gap in a range from 2.3 eV to 3.6 eV. ([0018] the filler particles #320 comprise Zinc Oxide. It is well established in the art that Zinc Oxide is a semiconductor material having a band gap within the claimed range of 2.3-3.6 eV)
Regarding Claim 20.
Tsai teaches A method for producing a semiconductor device, the method comprising:
arranging an intermediate layer (#100) on a chip carrier;
arranging a semiconductor chip (#200) on the intermediate layer; and
encapsulating the semiconductor chip with an encapsulation material (#300),
wherein filler particles (#320) are embedded in at least one of the intermediate layer or the encapsulation material,
Tsai does not explicitly disclose which are configured to increase at least one of an electrical conductivity of the intermediate layer or an electrical conductivity of the encapsulation material into a range from 10−16 S/m to 10−2 S/m upon an increase in an electric field strength to a value of more than 5 V/μm.
However, Onneby teaches the ZnO and SiC, identified as the preferred semiconducting filler materials, inherently produce nonlinear, field-dependent conductivity in polymer composites. And the onset of the nonlinear resistance is explicitly described as tunable through particle size selection and is shown in Fig.5 to increase with decreasing particle size, providing the skilled artisan with clear design guidance for achieving a threshold in the range around 5 V/um. And resistivity vs filler concentration data (Fig.2) demonstrates conductivity behavior spanning the broadly claimed 10−16 S/m to 10−2 S/m range. These limitations would have been obvious to one of ordinary skill in the art at the time of the invention because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et. al. (US-2021/0057298-A1, hereinafter Tsai), and further in view of Milano et. al. (US-2013/0020660-A1, hereinafter Milano).
Regarding Claim 15.
Tsai teaches The semiconductor device as claimed in claim 1,
Tsai does not explicitly disclose wherein:
the chip carrier comprises a current conductor that is configured to carry a measurement current, and the semiconductor chip is part of a current sensor that is configured to detect a strength of the measurement current.
However, Milano teaches in Fig.4C wherein:
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the chip carrier comprises a current conductor (#52a’) that is configured to carry a measurement current, and the semiconductor chip (#60) is part of a current sensor that is configured to detect a strength of the measurement current.([0049-0055])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Tsai’s semiconductor device with the teachings of Milano, as identified above, as combining the filed-grading filler particle with the current sensor package architecture would improve dielectric reliability in the current sensor package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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