DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 8, 9, 13-19, 25, and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohtsuki, US Patent 8,653,566
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Regarding claim 1, Ohtsuki teaches a photoelectric conversion device comprising:
a pixel substrate 101, wherein the pixel substrate includes:
a photoelectric conversion unit 105 configured to generate signal charge according to incident light,
a floating diffusion unit 110 configured to receive the signal charge as input,
a pixel transistor region 104 including the floating diffusion unit,
a first output line 111/112 configured to output a signal according to a potential of the floating diffusion unit,
a second output line 109a, 109b, 109c electrically connected to the first output line,
a first region, in a plan view relative to a main surface of the pixel substrate, where the first output line overlaps with at least a portion of the pixel transistor region (as labeled above), and
a second region, in the plan view relative to the main surface, located outside the first region and where the second output line overlaps with at least a portion of the photoelectric conversion unit (as labeled above), and wherein,
in the plan view relative to the main surface, an end portion of the second output line is positioned to overlap with at least a portion of the second region, and
wherein the end portion of the second output line 109b extends in a direction intersecting with respect to a longer-side direction of the second output line 109a, 109b (figure 2).
Regarding claim 2, Ohtsuki teaches in the plan view relative to the main surface, the floating diffusion unit is positioned to overlap with at least a portion of the first region (as labeled above).
Regarding claim 3, Ohtsuki teaches the pixel transistor region includes a transfer transistor 106 configured to transfer the signal charge to the floating diffusion unit, an amplifying transistor 107 configured to amplify the signal, and a reset transistor 108 configured to reset the floating diffusion unit (figure 2).
Regarding claim 5, Ohtsuki teaches in the plan view relative to the main surface, the floating diffusion unit 110 and wiring 111 connecting the floating diffusion unit and a gate of the amplifying transistor 107 are positioned to overlap with at least a portion of the first region (figure 2).
Regarding claim 8, Ohtsuki teaches the plan view relative to the main surface, the second output line 109c is positioned to overlap with at least a portion of the first output line 112 (figure 2).
Regarding claim 9, Ohtsuki teaches, in a cross-sectional view relative to the main surface, the second output line 109a is disposed between the first output line 111 and the photoelectric conversion unit 105 (Figure 2).
Regarding claim 13, Ohtsuki teaches 1, wherein, in a case where a pixel is disposed on the pixel substrate, the pixel includes the photoelectric conversion unit, the floating diffusion unit, and the pixel transistor region, and, in the plan view relative to the main surface, the second region is a region included in the pixel (figures 1and 2)
Regarding claim 14, Ohtsuki teaches a plurality of pixels (all located in the pixel array) including the pixel, are disposed in a matrix, and, for each of columns where the plurality of pixels are disposed, a plurality of the first output lines is disposed (figure 1)
Regarding claim 15, Ohtsuki teaches in the plan view relative to the main surface, the second output line 109b is positioned not to overlap with the floating diffusion unit (figure 2).
Regarding claim 16, Ohtsuki teaches the pixel transistor region includes an amplifying transistor 107 configured to amplify the signal, and, in the plan view relative to the main surface, the second output line 109a or 109b is positioned not to overlap with wiring 111 connecting the floating diffusion unit and a gate of the amplifying transistor (figure 2).
Regarding claims 17-18, Ohtsuki teaches a wiring layer 109 is disposed on one side of two sides of the pixel substrate, and light is incident on the photoelectric conversion unit from the other side of the two sides of the pixel substrate (left side of figure 2), further comprising a circuit substrate 103, stacked on the one side of the pixel substrate, includes a peripheral circuit configured to process a signal output by the first output line (figure 1).
Regarding claim 19, Ohtsuki teaches a photoelectric conversion device comprising:
a pixel substrate 101 having a first pixel and a second pixel, wherein the first pixel and the second pixel each include:
a photoelectric conversion unit 105 configured to generate signal charge according to incident light,
a floating diffusion unit 110 configured to receive the signal charge as input, and
a pixel transistor region 104 including the floating diffusion unit, wherein the pixel substrate further includes:
a first output line 111 configured to output a signal according to a potential of the floating diffusion unit,
a second output line 109a, 109b, 109c electrically connected to the first output line where the first pixel and the second pixel are adjacent to each other in a longer-side direction of the second output line (Note: as shown in figure 1, there would be pixels that exist to the right or below pixel 104 in figure 1),
a first region, in a plan view relative to a main surface of the pixel substrate,
where the first output line overlaps with at least a portion of the pixel transistor region of the first pixel (as shown in figure above), and
a third region, in the plan view relative to the main surface, located outside the first region and located between the pixel transistor region included in the first pixel and the pixel transistor region included in the second pixel (Note: the third region is the region of 101 in figure 1 between the dashed lines that represents 104), and
wherein, in the plan view relative to the main surface, an end portion of the second output line 109a, 109b intersecting with respect to the longer-side direction of the second output line is positioned to overlap with at least a portion of the third region, and wherein the end portion 109c of the second output line extends in a direction intersecting with respect to a longer-side direction of the second output line (figure 2).
Regarding claim 25, Ohtsuki teaches the pixel transistor region includes a transfer transistor 106 configured to transfer the signal charge to the floating diffusion unit, and an amplifying transistor 107 configured to amplify the signal, and wherein, in the plan view relative to the main surface, the floating diffusion unit and the amplifying transistor are disposed on a straight line along a longer-side direction of the second output line 109a, 109b (shown as arrow A below), and the floating diffusion unit and the transfer transistor are disposed on a straight line along a shorter-side direction of the second output line 109a (shown as arrow B below).
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Regarding claim 27, Ohtsuki teaches equipment comprising: the photoelectric conversion device according to claim 1, wherein the equipment further comprises at least one of:
an optical device configured to direct light to the photoelectric conversion device, a control device configured to control the photoelectric conversion device, a processing device 103 configured to process a signal output from the photoelectric conversion device, a display device configured to display information obtained by the photoelectric conversion device, a storage device configured to store information obtained by the photoelectric conversion device, and a mechanical device configured to operate based on information obtained by the photoelectric conversion device (figure 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohtsuki as applied to claim 19 above, and further in view of Lee, US Patent 7,663,194.
Regarding claim 20, while Ohtsuki teaches a first pixel includes a first photoelectric conversion unit, Ohtsuki fails to teach a third photoelectric conversion unit, and the first photoelectric conversion unit and the third photoelectric conversion unit share the floating diffusion unit included in the first pixel.
Lee teaches a third photoelectric conversion unit 201, and the first photoelectric conversion unit 200 and the third photoelectric conversion unit share the floating diffusion unit 205 included in the first pixel. (figure 2B) by teaching the use of multiple photodiodes within a pixel area. This multiple photodiode structure allow for securing enough number of unit pixels and an enough photodiode region with a reduced size, which improves the electronic device formed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee with that of Ohtsuki because a multiple photodiode structure allow for securing enough number of unit pixels and an enough photodiode region with a reduced size, which improves the electronic device formed.
Regarding claim 22, Lee teaches in the plan view relative to the main surface, the floating diffusion unit included in the first pixel is disposed between the first photoelectric conversion unit and the third photoelectric conversion unit (figure 3B).
Regarding claim 23, Lee teaches the pixel transistor region includes an amplifying transistor 205 configured to amplify the signal, and the floating diffusion unit and a gate of the amplifying transistor are connected via wiring (figure 2A).
Regarding claim 24, while Ohtsuki teaches the first pixel includes a first photoelectric conversion unit and the pixel transistor region includes an amplifying transistor configured to amplify the signal, and the amplifying transistor has a gate connected to the floating diffusion unit (figure 1), Ohtsuki fails to teach a third photoelectric conversion unit, wherein the signal charge corresponding to the first photoelectric conversion unit and the signal charge corresponding to the third photoelectric conversion unit are input to the gate.
Lee teaches a third photoelectric conversion unit 201 (figure 2B) by teaching the use of multiple photodiodes within a pixel area. This multiple photodiode structure allow for securing enough number of unit pixels and an enough photodiode region with a reduced size, which improves the electronic device formed. Further, Lee teaches wherein the signal charge corresponding to the first photoelectric conversion unit and the signal charge corresponding to the third photoelectric conversion unit are input to the gate (of 205 in figure 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee with that of Ohtsuki because a multiple photodiode structure allow for securing enough number of unit pixels and an enough photodiode region with a reduced size, which improves the electronic device formed.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohtsuki and Lee as applied to claim 20 above, and further in view of Ha et al, US Patent 8,895,936
Regarding claim 21, Ohtsuki and Lee fail to teach a plurality of microlenses, wherein one of the plurality of microlenses is disposed corresponding to the first photoelectric conversion unit, and another one of the plurality of microlenses is disposed corresponding to the third photoelectric conversion unit.
However, Ha teaches a more complete pixel device, which includes a plurality of microlenses 144, wherein one of the plurality of microlenses is disposed corresponding to the first photoelectric conversion unit 120 (left side), and another one of the plurality of microlenses 144 is disposed corresponding to the third photoelectric conversion unit 120 (right side).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ha with that of Ohtsuki and Lee because microlenses are commonly used with photodiodes to concentrate the incoming light to the photodiode, which improves the electric output of the photodiode.
Allowable Subject Matter
Claims 4, 6, 7, 10-12, 16, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to 35 USC 112 rejection have been fully considered and are persuasive. The 35 USC 112 rejection has been withdrawn.
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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