DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 03/18/2026 amendments of paragraphs [0052], [0066], [0072], [0075], [0100] and [0105] of the specification of the instant application has been noted and entered.
Election/Restrictions
Applicant’s election without traverse of Invention A Species A-1 drawn to Fig (1A) and corresponding to claims 1-9 and 22 in the reply filed on 03/18/2026 is acknowledged.
Claims 10-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/18/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/13/2023 and 11/22/2024 was filed after the mailing date of the application on 10/13/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-8 are rejected under 35 U.S.C. 102(a)1 as being anticipated by Chi, US 20080145985 A1 (Chi).
Regarding claim 1; Chi teaches A unit cell comprising:
an active layer (Chi: Annotated Fig (4D) shared in this OA: 14’) including a first junction region (12’), a second junction region (12’) and a channel (Channel, [0014]: “… the respective source/drain regions may be electrically connected through conductive channels formed in the semiconductor substrate”) between the first junction region (12’) and the second junction region (12’);
a separation region (Separation Region) formed in the active layer (Active Layer) to separate the first junction region (12’) and the channel (Channel) into at least two portions (First and Second Portions); and
a gate (17’+18’+21’) arranged in the separation region (Separation Region).
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Regarding claim 2; Chi teaches all the limitations of the unit cell of claim 1.
Further, Chi teaches wherein the separation region (Chi: Annotated Fig (4D): Separation Region: 15’) comprises an insulation material ([0119]: “… in the gate dielectric layer 15'…”).
Regarding claim 5; Chi teaches all the limitations of the unit cell of claim 1.
Further, Chi teaches wherein the gate (Chi: Annotated Fig (4D): 17’+18’+21’) is extended vertically by a surface of the active layer (14’).
Regarding claim 6; Chi teaches all the limitations of the unit cell of claim 5.
Further, Chi teaches wherein the gate (Chi: Annotated Fig (4D) shared in this OA: 17’+18’+21’) comprises at least one or more of a silicon layer ([0118]: “… a gate structure 17' and a silicon oxide layer 18' are formed on the gate dielectric layer 15'…”), a metal layer, a metal nitride layer, a metal silicide layer and a combination thereof.
Regarding claim 7; Chi teaches all the limitations of the unit cell of claim 1.
Chi teaches further comprising a gate insulation layer (Chi: Annotated Fig (4D) shared in this OA: 15’) positioned on the gate (17’+18’+21’).
Regarding claim 8; Chi teaches all the limitations of the unit cell of claim 1.
Chi teaches further comprising a storage element that includes a storage node (Chi: Annotated Fig (4D) shared in this OA: 16’) electrically connected to an end of the second junction region (12’).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitation indicate claim limitations that are not explicitly disclosed by the primary reference but are disclosed by the secondary reference(s)
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chi, US 20080145985 A1 (Chi) in view of Ahn et al, US 20130170303 A1 (Ahn).
Regarding claim 3; Chi teaches all the limitations of the unit cell of claim 1.
However, Chi does not teach further comprising a bit line connected to an end of the first junction region.
Ahn teaches further comprising a bit line (Ahn: Annotated Fig (1A) shared in this OA: BL) connected to an end of the first junction region (DSL_0).
Chi and Ahn are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to connect the first junction region to a bit line to facilitate controlling the memory device leading to a more reliable device.
Regarding claim 4; Chi in view of Ahn teach all the limitations of the unit cell of claim 3
Chi does not teach wherein a length of the separation region between the gate and the bit line is equal to or longer than a distance between the gate and the second junction region.
However, Ahn teaches wherein a length (Ahn: Annotated Fig (1A) shared in this OA: D1) of the separation region between the gate (WL_N) and the bit line (BL) is equal to or longer than a distance (D2) between the gate (WL_N) and the second junction region (DSL_1).
Chi and Ahn are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chi by constructing the distances between the gate and the bit line and the second junction region to be as disclosed in Ahn to improve the isolation of the gate from any cross talk to the but line or the junction and thus increasing the reliability of the device.
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Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chi, US 20080145985 A1 (Chi) in view of Im, US 20230171946 A1 (Im).
Regarding claim 9; Chi teaches all the limitations of the unit cell of claim 8.
Chi does not teach wherein a distance between the gate and the storage node is substantially equal to or longer than a length of the separation region between the gate and a bit line.
However, Im teaches wherein a distance (Im: Annotated Fig (15) shared in this OA: D3) between the gate (15+16) and the storage node (26’) is substantially equal to or longer than a length (D4) of the separation region between the gate (15+16) and a bit line (20).
Chi an Im are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chi by constructing the distances between the gate and the storage node and the bit line as disclosed in Im to improve the isolation of the different components of the device against cross talk and thus improving the performance of the device.
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Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Onuki et al, WO 2020170067 A1 (Onuki) in view of Ahn et al, US 20130170303 A1 (Ahn).
Regarding claim 22; Chi teaches a unit cell for a three-dimensional semiconductor device comprising:
an active layer (Onuki: Annotated Fig (14A)shared in this OA: 230) including a first junction region (Area under 243a, Source/Drain), a second junction region (Area under 243b, Source/Drain) and a channel (230) between the first junction region (Area under 243a, Source/Drain) and the second junction region (Area under 243b, Source/Drain);
a separation region (Separation Region) formed in the active layer (230) to separate the first junction region (Area under 243a, Source/Drain) and the channel (Channel) into at least two portions (First and Second Portion); and
a gate (260) arranged in the separation region (Separation Region), extending vertically beyond the separation region (Separation Region) for connection to other active layers above the active layer.
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While Onuki teaches a memory unit with junction regions, separation region, and a gate in the active layer, and mentions the possibility of the different active layers being connected through the gate contact (see Page:13 Lines: 4-6 of the translated copy of Onuki attached to this OA: “In addition, the conductor 426 is preferably electrically connected to the transistor 200T through a conductor 428 which is electrically connected to any one of a source, a drain, and a gate of the transistor 200T.”) it fails to explicitly show how the gate is connected to other active layers above the active layer. In other words, Onuki fails to teach for connection to other active layers above the active layer.
However, Ahn teaches for connection (Ahn Annotated Fig (1A) shared in this OA: WL_N) to other active layers (C) above the active layer (C).
Onuki and Ahn are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person of ordinary skill in the art, to modify Onuki by using the gate to connect to other active layers above the active layer to allow for 3D integration of transistors on the chip die which increases the density of transistors per unit area of the chip leading to a better and faster performing device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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