Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The corrections to the drawings in the response filed on June 19, 2026 are accepted by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3 and 7-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “wherein the respective three-dimensional structure comprises at least one of a trench, a cup, a nanowire, nanoparticles, or a surface of a porous material,” on page 2 lines 10-11. This limitation renders claim 2 indefinite because it is unclear how the respective three-dimensional structure can have more than one of the listed structures. The examiner notes that while the structure of each individual element of a trench, a cup, a nanowire, nanoparticles, or a surface of a porous material is clear, the claim language also includes combinations of the individual elements. The examiner next notes the structures of the individual elements as well as the combinations of the individual elements must be clear and it is unclear what structures correspond to the combinations of the individual elements. For example, it is unclear what structure corresponds to the combination of a trench, a nanowire, and a porous material because it is unclear how the respective three-dimensional structure can be all of a trench, a nanowire, and a porous material. For examination purposes, this limitation will be interpreted as wherein the respective three-dimensional structure has a structure selected from the group consisting of a trench, a cup, a nanowire, nanoparticles, or a surface of a porous material.
Claim 3 recites the limitation “wherein the second electrically conductive electrode conformally covers the second functional layer,” on page 4 lines 14-15. There is insufficient antecedent basis for this limitation in the claim because a second electrically conductive electrode and a second function layer have been deleted from claim 1, which claim 3 depends from. For examination purposes, claim 3 will be treated as not reciting the above limitation.
Claim 7 recites the limitations “the second metal nitride,” on page 5 line 6 and “the second metal-oxynitride,” on page 5 line 7. There is insufficient antecedent basis for these limitations in the claim because a second metal nitride and a second metal-oxynitride have been deleted from claim 1, which claim 7 depends from. For examination purposes, claim 7 will be treated as not reciting the above limitations.
Claim 8 recites the limitation “the second functional layer,” on page 5 line 11. There is insufficient antecedent basis for this limitation in the claim because a second functional layer has been deleted from claim 1, which claim 8 depends from. For examination purposes, claim 8 will be treated as not reciting the above limitation.
Claim 9 recites the limitation “the second metal nitride,” on page 5 line 15. There is insufficient antecedent basis for this limitation in the claim because a second metal nitride has been deleted from claim 1, which claim 9 depends from. For examination purposes, claim 9 will be treated as not reciting the above limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6, 8-9, 22-23, and 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0389324) hereinafter Chen ‘324 in view of Lin (US 2022/0328508).
Regarding Claim 1:
Chen ‘324 discloses a memory cell arrangement, comprising:
a substrate (substrate for memory array, See fig. 1, ref. no. 120, fig. 3B, ref. no. 132, paragraphs 21, 26-27, and 37) comprising a plurality of three-dimensional structures (deep trenches formed in substrate, See fig. 3B and paragraph 26. The examiner notes that the storage element shown in figure 3B is a representative example of one storage element of one memory cell of the memory array and that the substrate for the memory array will include a plurality of deep trenches because the memory array includes a plurality of memory cells);
a plurality of memory cells (plurality of 1T1F memory cells, See figs. 1, 4A, ref. no. 125, paragraph 21, 23, 41); and
a plurality of sets of control lines (bit lines, source lines, and word lines for selecting a 1T1F memory cell, See paragraph 23 and 41) for selectively addressing one or more memory cells of the plurality of memory cells;
wherein each memory cell of the plurality of memory cells comprises a memory layer stack (bottom electrode, interfacial layer, seed layer, ferroelectric film, and top electrode, See fig. 3B, ref. no. 134, 136, 138, 140, 142, and paragraphs 29-33) disposed over a respective three-dimensional structure of the plurality of three-dimensional structures,
wherein the substrate comprises an oxide layer (dielectric layer of Aluminum Oxide Al2O3, See fig. 3B, ref. no. 133 and paragraph 37) at an interface to the memory layer stack.
Chen ‘324 does not disclose the memory layer stack comprising:
a first electrode;
a memory element disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides; and
a second electrode disposed over the memory element, wherein the first electrode, the second electrode, and the memory element form a memory capacitor;
wherein the first electrode comprises a first electrically conductive electrode layer substantially consisting of a first metal and a first functional layer substantially consisting of a first metal nitride or a first metal-oxynitride,
wherein the first electrically conductive electrode layer is disposed between the first function layer; and
wherein the first electrode further comprises a further first functional layer substantially consisting of the first metal nitride or the first metal-oxynitride, wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer.
Lin the memory layer stack comprising:
a first electrode (bottom electrode interface structure, bottom electrode, bottom electrode barrier layer, fig. 2C, ref. nos. 104, 106, 112, paragraphs 20-21, 47, and 53);
a memory element (switching layer, fig. 2C, ref. no. 108, paragraphs 21 and 39) disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides (hafnium oxide-based film, zirconium oxide-based film, or hafnium zirconium oxide, See paragraph 39); and
a second electrode (top electrode interface structure, top electrode, top electrode barrier layer, fig. 2C, ref. no. 114, 202, 206, paragraphs 20-21, 47, and 53-55) disposed over the memory element, wherein the first electrode, the second electrode, and the memory element form a memory capacitor (the bottom electrode interface structure, bottom electrode, bottom electrode barrier layer, switching layer, top electrode interface structure, top electrode, and top electrode barrier layer form a capacitor structure, See fig. 2C, ref. nos. 104, 106, 112, 108, 114, 202, and 206);
wherein the first electrode comprises a first electrically conductive electrode layer substantially consisting of a first metal (bottom electrode made of molybdenum, See fig. 2C, ref. no. 106 and paragraph 35) and a first functional layer substantially consisting of a first metal nitride (bottom electrode barrier layer made of tantalum nitride, See fig. 2C, ref. no. 112 and paragraph 38) or a first metal-oxynitride,
wherein the first electrically conductive electrode layer is disposed between the first function layer and the memory element (the bottom electrode is disposed between the bottom electrode barrier layer and the switching layer, See fig. 2C, ref. nos. 106, 108, 112); and
wherein the first electrode further comprises a further first functional layer substantially consisting of the first metal nitride (bottom electrode interface structure made of tantalum nitride, See fig. 2C, ref. no. 104 and paragraph 41) or the first metal-oxynitride, wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer (the bottom electrode interface structure is disposed between and in direct contact with the switching layer and the bottom electrode, See fig. 2C, ref. nos. 104, 106, and 108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 to replace the memory layer stack with the memory layer stack comprising a first electrode, a memory element disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides, and a second electrode disposed over the memory element, wherein the first electrode, the second electrode, and the memory element form a memory capacitor, wherein the first electrode comprises a first electrically conductive electrode layer substantially consisting of a first metal and a first functional layer substantially consisting of a first metal nitride or a first metal-oxynitride, wherein the first electrically conductive electrode layer is disposed between the first function layer, and wherein the first electrode further comprises a further first functional layer substantially consisting of the first metal nitride or the first metal-oxynitride, wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer as taught by Lin in order enhance memory cell retention. (See Lin paragraphs 17-18.)
Regarding Claim 2:
Chen ‘324 discloses wherein the respective three-dimensional structure comprises at least one of a trench (deep trenches formed in substrate, See fig. 3B and paragraph 26), a cup, a nanowire, nanoparticles, or a surface of a porous material.
Regarding Claim 6:
Lin discloses wherein the one or more transition-metal-oxides of the memory element are hafnium oxide (hafnium oxide-based film, See paragraph 39), zirconium oxide (zirconium oxide-based film, See paragraph 39), or hafnium zirconium oxide (hafnium zirconium oxide, See paragraph 39).
Regarding Claim 8:
Lin discloses wherein the first functional layer has a thickness greater than 1nm (Lin discloses the thickness of bottom electrode barrier layer is 1.97nm-19.70nm, See fig. 2C, ref. nos. Tbe, 106, 112, and paragraph 35. The examiner notes that the thickness of the bottom electrode barrier layer is calculated by taking the endpoints of the range of thickness of the bottom electrode Tbe 5nm-50nm and multiplying the endpoints by the ratio of thicknesses (0.13in/0.33in) the bottom electrode Tbe and bottom electrode barrier layer as shown in figure 2C).
Regarding Claim 9:
Lin discloses wherein the first metal nitride and/or the second metal nitride is one of: titanium nitride, tungsten nitride, molybdenum nitride, tantalum nitride (tantalum nitride, See paragraphs 38 and 41), niobium nitride, hafnium nitride, or zirconium nitride.
Regarding Claim 22:
Chen ‘324 discloses a memory cell arrangement, comprising:
a substrate (substrate for memory array, See fig. 1, ref. no. 120, fig. 3B, ref. no. 132, paragraphs 21, 26-27, and 37) comprising a plurality of three-dimensional structures (deep trenches formed in substrate, See fig. 3B and paragraph 26. The examiner notes that the storage element shown in figure 3B is a representative example of one storage element of one memory cell of the memory array and that the substrate for the memory array will include a plurality of deep trenches because the memory array includes a plurality of memory cells);
a plurality of memory cells (plurality of 1T1F memory cells, See figs. 1, 4A, ref. no. 125, paragraph 21, 23, 41); and
a plurality of sets of control lines (bit lines, source lines, and word lines for selecting a 1T1F memory cell, See paragraph 23 and 41) for selectively addressing one or more memory cells of the plurality of memory cells;
wherein each memory cell of the plurality of memory cells comprises a memory layer stack (bottom electrode disposed over the substrate, interfacial layer, seed layer, ferroelectric film, and top electrode, See fig. 3B, ref. no. 132, 134, 136, 138, 140, 142, and paragraphs 29-33) at a respective three-dimensional structure of the plurality of three-dimensional structures,
Chen ‘324 does not disclose the memory layer stack comprising:
a first electrode disposed over the substrate;
a memory element disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides; and
a second electrode disposed over the memory element, wherein the first electrode, the second electrode, and the memory element form a memory capacitor;
wherein the second electrode comprises a second electrically conductive electrode layer substantially consisting of a second metal, and a second functional layer substantially consisting of a second metal nitride or a second metal-oxynitride,
wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer,
wherein the second functional layer is disposed in direct contact with the memory element, and
wherein the second electrode further comprises a further second functional layer substantially consisting of the second metal nitride or the second metal-oxynitride,
wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer.
Lin the memory layer stack comprising:
a first electrode (bottom electrode interface structure, bottom electrode, bottom electrode barrier layer, fig. 2C, ref. nos. 104, 106, 112, paragraphs 20-21, 47, and 53);
a memory element (switching layer, fig. 2C, ref. no. 108, paragraphs 21 and 39) disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides (hafnium oxide-based film, zirconium oxide-based film, or hafnium zirconium oxide, See paragraph 39); and
a second electrode (top electrode interface structure, top electrode, top electrode barrier layer, fig. 2C, ref. no. 114, 202, 206, paragraphs 20-21, 47, and 53-55) disposed over the memory element, wherein the first electrode, the second electrode, and the memory element form a memory capacitor (the bottom electrode interface structure, bottom electrode, bottom electrode barrier layer, switching layer, top electrode interface structure, top electrode, and top electrode barrier layer form a capacitor structure, See fig. 2C, ref. nos. 104, 106, 112, 108, 114, 202, and 206);
wherein the second electrode comprises a second electrically conductive electrode layer substantially consisting of a second metal (top electrode made of molybdenum, See fig. 2C, ref. no. 114 and paragraph 46), and a second functional layer (top electrode interface structure, See fig. 2C, ref. no. 202, paragraph 41 and 53-55) substantially consisting of a second metal nitride (tantalum nitride, See paragraph 41) or a second metal-oxynitride (tantalum oxynitride, See paragraph 41),
wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer (the top electrode interface structure is disposed between the top electrode and the switching layer, See fig. 2C, ref. nos. 108, 114, 202),
wherein the second functional layer is disposed in direct contact with the memory element (the top electrode interface structure is disposed in direct contact with the switching layer, See fig. 2C, ref. nos. 108, 202), and
wherein the second electrode further comprises a further second functional layer substantially consisting of the second metal nitride (top electrode barrier layer made of tantalum nitride, See fig. 2C, ref. no. 206, paragraphs 38 and 53-55) or the second metal-oxynitride,
wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer (the top electrode barrier layer is disposed direction on the top electrode, See fig. 2C, ref. nos. 114, 206).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 to replace the memory layer stack with the memory layer stack comprising a first electrode disposed over the substrate, a memory element disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides, a second electrode disposed over the memory element, wherein the first electrode, the second electrode, and the memory element form a memory capacitor, wherein the second electrode comprises a second electrically conductive electrode layer substantially consisting of a second metal, and a second functional layer substantially consisting of a second metal nitride or a second metal-oxynitride, wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer, wherein the second functional layer is disposed in direct contact with the memory element, wherein the second electrode further comprises a further second functional layer substantially consisting of the second metal nitride or the second metal-oxynitride, and wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer as taught by Lin in order enhance memory cell retention. (See Lin paragraphs 17-18 and 54.)
The examiner notes that the feature of a first electrode disposed over the substrate is taught by the combination of Chen ‘324 and Lin because the first electrode taught by Lin will be disposed over the substrate taught by Chen ‘324.
Regarding Claim 23:
Lin discloses wherein the second electrically conductive electrode conformally covers the second functional layer (the top electrode conformally covers the top electrode interface structure, See Lin fig. 2C, ref. nos. 114 and 202).
Regarding Claim 25:
Lin discloses wherein the second functional layer has a thickness greater than 1nm (Lin discloses the thickness of top electrode interface structure is 5.30nm-50.03nm, See fig. 2C, ref. nos. Tbe, 106, 202, and paragraph 35. The examiner notes that the thickness of the top electrode interface structure is calculated by taking the endpoints of the range of thickness of the bottom electrode Tbe 5nm-50nm and multiplying the endpoints by the ratio of thicknesses (0.35in/0.33in) the top electrode interface structure and the bottom electrode Tbe as shown in figure 2C).
Regarding Claim 26:
Lin discloses wherein the second metal nitride is one of: titanium nitride, tungsten nitride, molybdenum nitride, tantalum nitride (tantalum nitride, See paragraphs 38, 41, and 53-55), niobium nitride, hafnium nitride, or zirconium nitride.
Regarding Claim 27:
Chen ‘324 discloses a memory cell comprising:
a substrate portion (substrate for memory array, See fig. 1, ref. no. 120, fig. 3B, ref. no. 132, paragraphs 21, 26-27, and 37) comprising a three-dimensional structure (deep trench formed in substrate, See fig. 3B and paragraph 26);
a memory layer stack (bottom electrode disposed over the substrate portion, interfacial layer, seed layer, ferroelectric film, and top electrode, See fig. 3B, ref. no. 132, 134, 136, 138, 140, 142, and paragraphs 29-33) at the three-dimensional structure.
Chen ‘324 does not disclose the memory layer stack comprising:
a first electrode disposed over the substrate portion;
a memory element disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides; and
a second electrode disposed over the memory element,
wherein the first electrode, the second electrode, and the memory element form a memory capacitor;
wherein the first electrode comprises a first electrically conductive electrode layer substantially consisting of a first metal, a first functional layer substantially consisting of a first metal nitride or a first metal-oxynitride, and a further first functional layer substantially consisting of the first metal nitride or the first metal-oxynitride, wherein the first electrically conductive electrode layer is disposed between the first functional layer and the memory element, wherein the first electrically conductive electrode layer is disposed in direct contact with the first functional layer, and wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer; and/or
wherein the second electrode comprises a second electrically conductive electrode layer substantially consisting of a second metal, a second functional layer substantially consisting of a second metal nitride or a second metal-oxynitride, and a further second functional layer substantially consisting of the second metal nitride or the second metal- oxynitride, wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer, wherein the second functional layer is disposed in direct contact with the memory element, and wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer.
Lin discloses the memory layer stack comprising:
a first electrode (bottom electrode interface structure, bottom electrode, bottom electrode barrier layer, fig. 2C, ref. nos. 104, 106, 112, paragraphs 20-21, 47, and 53);
a memory element (switching layer, fig. 2C, ref. no. 108, paragraphs 21 and 39) disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides (hafnium oxide-based film, zirconium oxide-based film, or hafnium zirconium oxide, See paragraph 39); and
a second electrode (top electrode interface structure, top electrode, top electrode barrier layer, fig. 2C, ref. no. 114, 202, 206, paragraphs 20-21, 47, and 53-55) disposed over the memory element,
wherein the first electrode, the second electrode, and the memory element form a memory capacitor (the bottom electrode interface structure, bottom electrode, bottom electrode barrier layer, switching layer, top electrode interface structure, top electrode, and top electrode barrier layer form a capacitor structure, See fig. 2C, ref. nos. 104, 106, 112, 108, 114, 202, and 206);
wherein the first electrode comprises a first electrically conductive electrode layer substantially consisting of a first metal (bottom electrode made of molybdenum, See fig. 2C, ref. no. 106 and paragraph 35), a first functional layer substantially consisting of a first metal nitride (bottom electrode barrier layer made of tantalum nitride, See fig. 2C, ref. no. 112 and paragraph 38) or a first metal-oxynitride, and a further first functional layer substantially consisting of the first metal nitride (bottom electrode interface structure made of tantalum nitride, See fig. 2C, ref. no. 104 and paragraph 41) or the first metal-oxynitride, wherein the first electrically conductive electrode layer is disposed between the first functional layer and the memory element (the bottom electrode is disposed between the bottom electrode barrier layer and the switching layer, See fig. 2C, ref. nos. 106, 108, 112), wherein the first electrically conductive electrode layer is disposed in direct contact with the first functional layer (the bottom electrode is disposed in direct contact with the bottom electrode barrier layer, See fig. 2C, ref. nos. 106 and 112), and wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer (the bottom electrode interface structure is disposed between and in direct contact with the switching layer and the bottom electrode, See fig. 2C, ref. nos. 104, 106, and 108); and
wherein the second electrode comprises a second electrically conductive electrode layer substantially consisting of a second metal (top electrode made of molybdenum, See fig. 2C, ref. no. 114 and paragraph 46), a second functional layer (top electrode interface structure, See fig. 2C, ref. no. 202, paragraph 41 and 53-55) substantially consisting of a second metal nitride (tantalum nitride, See paragraph 41) or a second metal-oxynitride (tantalum oxynitride, See paragraph 41), and a further second functional layer substantially consisting of the second metal nitride (top electrode barrier layer made of tantalum nitride, See fig. 2C, ref. no. 206, paragraphs 38 and 53-55) or the second metal- oxynitride, wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer (the top electrode interface structure is disposed between the top electrode and the switching layer, See fig. 2C, ref. nos. 108, 114, 202), wherein the second functional layer is disposed in direct contact with the memory element (the top electrode interface structure is disposed in direct contact with the switching layer, See fig. 2C, ref. nos. 108 and 202), and wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer (the top electrode barrier layer is disposed direction on the top electrode, See fig. 2C, ref. nos. 114, 206).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 to replace the memory layer stack with the wherein the first electrode comprises a first electrically conductive electrode layer substantially consisting of a first metal, a first functional layer substantially consisting of a first metal nitride or a first metal-oxynitride, and a further first functional layer substantially consisting of the first metal nitride or the first metal-oxynitride, wherein the first electrically conductive electrode layer is disposed between the first functional layer and the memory element, wherein the first electrically conductive electrode layer is disposed in direct contact with the first functional layer, and wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer; and wherein the second electrode comprises a second electrically conductive electrode layer substantially consisting of a second metal, a second functional layer substantially consisting of a second metal nitride or a second metal-oxynitride, and a further second functional layer substantially consisting of the second metal nitride or the second metal- oxynitride, wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer, wherein the second functional layer is disposed in direct contact with the memory element, and wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer as taught by Lin in order enhance memory cell retention. (See Lin paragraphs 17-18 and 54.)
Claims 3 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2023/0389324) in view of Lin (US 2022/0328508) further in view of Gong et al. (US 2024/0074207).
Regarding Claim 3:
The above stated combination of Chen ‘324 and Lin discloses the above stated memory cell arrangement. The above stated combination of Chen ‘324 and Lin further discloses wherein the first electrically conductive electrode conformally covers the first functional layer (the bottom electrode conformally covers a bottom electrode barrier layer, See Lin fig. 2C, ref. nos. 106 and 112); and wherein the respective three-dimensional structure has an aspect ratio equal to or greater than six (the aspect ratio of the deep trench ranges from about 5 to about 30, See Chen ‘324 paragraph 27).
The above stated combination of Chen ‘324 and Lin does not disclose wherein the respective three-dimensional structure has a width equal to or less than 200nm.
Gong discloses a ferroelectric random-access memory cell having a width between 10-1000nm (See fig. 10, ref. no. 122 and paragraph 66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Lin to include the respective three-dimensional structure has a width equal to or less than 200nm as taught by Gong in order increase memory density of the memory array by reducing the width of the storage elements.
Regarding Claim 21:
The above stated combination of Chen ‘324 and Lin discloses the above stated memory cell arrangement. The above stated combination of Chen ‘324 and Lin further discloses wherein the respective three-dimensional structure has an aspect ratio equal to or greater than six (the aspect ratio of the deep trench ranges from about 5 to about 30, See Chen ‘324 paragraph 27).
The above stated combination of Chen ‘324 and Lin does not disclose wherein the respective three-dimensional structure has a width equal to or less than 200nm.
Gong discloses a ferroelectric random-access memory cell having a width between 10-1000nm (See fig. 10, ref. no. 122 and paragraph 66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Lin to include the respective three-dimensional structure has a width equal to or less than 200nm as taught by Gong in order increase memory density of the memory array by reducing the width of the storage elements.
The examiner also notes it has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Claim 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘324 et al. (US 2023/0389324) in view of Lin (US 2022/0328508) further in view of Chen et al. (US 2021/0035992) hereafter Chen ‘992.
Regarding Claim 4:
The above stated combination of Chen ‘324 and Lin discloses the above stated memory cell arrangement. The examiner notes that Chen ‘324 discloses an inter-layer dielectric formed from silicon dioxide deposited over the top electrode of the storage element. (See fig. 3B, ref. no. 156 and paragraph 34).
The above stated combination of Chen ‘324 and Lin does not disclose wherein the oxide layer substantially consists of silicon oxide.
Chen ‘992 discloses a lower insulating structure formed from silicon dioxide formed around a bottom electrode of tungsten and titanium nitride of a FeRam device (See fig. 2A, ref. no. 110, and paragraphs 25, 28, and 32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Lin to replace the dielectric layer of Aluminum Oxide Al2O3 with a dielectric layer of silicon dioxide as taught by Chen ‘992 in order to simply fabrication of the memory array by reducing the number of different material used for fabrication.
Regarding Claim 5:
Chen ‘324 discloses wherein the respective three-dimensional structure is a trench disposed within the oxide layer or wherein the respective three-dimensional structure is a trench disposed within the substrate and conformally covered with one or more oxide layers (the deep trench in the substrate is conformally covered by the dielectric layer. See Chen ‘324 fig. 3B, ref. nos. 132, 133 and paragraph 37).
Claims 7, 9, 24, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Chen ‘324 et al. (US 2023/0389324) and Lin (US 2022/0328508) in view of Hu (US2021/0091096).
Regarding Claim 7:
The above stated combination of Chen ‘324 and Lin discloses the above stated memory cell arrangement.
The above stated combination of Chen ‘324 and Lin does not disclose wherein the first metal nitride is tungsten nitride and/or wherein the first metal-oxynitride is tungsten-oxynitride.
Hu discloses wherein the first metal nitride is tungsten nitride (materials for the bottom electrode of a memory capacitor can include tungsten nitride, See fig. 1, ref. no. 110 and paragraph 47) and/or wherein the first metal-oxynitride is tungsten-oxynitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Lin to use tungsten nitride for the first metal nitride as taught by Hu since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding Claim 9:
The above stated combination of Chen ‘324 and Lin discloses the above stated memory cell arrangement.
The above stated combination of Chen ‘324 and Lin does not disclose wherein the first metal nitride is one of: titanium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium nitride, or zirconium nitride.
Hu discloses wherein the first metal nitride is one of: titanium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium nitride, or zirconium nitride (materials for the bottom electrode of a memory capacitor can include titanium nitride, tungsten nitride, See fig. 1, ref. no. 110 and paragraph 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Lin to use titanium nitride or tungsten nitride for the first metal nitride as taught by Hu since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding Claim 24:
The above stated combination of Chen ‘324 and Lin discloses the above stated memory cell arrangement.
The above stated combination of Chen ‘324 and Lin does not disclose wherein the second metal nitride is tungsten nitride and/or wherein the second metal-oxynitride is tungsten-oxynitride.
Hu discloses wherein the second metal nitride is tungsten nitride (materials for the top electrode of a memory capacitor can in tungsten nitride, See fig. 1, ref. no. 112 and paragraph 47) and/or wherein the first metal-oxynitride is tungsten-oxynitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Lin to use tungsten nitride for the second metal nitride as taught by Hu since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding Claim 26:
The above stated combination of Chen ‘324 and Lin discloses the above stated memory cell arrangement.
The above stated combination of Chen ‘324 and Lin does not disclose wherein the second metal nitride is one of: titanium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium nitride, or zirconium nitride.
Hu discloses wherein the second metal nitride is one of: titanium nitride, tungsten nitride, molybdenum nitride, niobium nitride, hafnium nitride, or zirconium nitride (materials for the top electrode of a memory capacitor can include titanium nitride, tungsten nitride, See fig. 1, ref. no. 112 and paragraph 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Lin to use titanium nitride or tungsten nitride for the second metal nitride as taught by Hu since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960).
Response to Arguments
Applicant’s arguments with respect to claims 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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