Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of claims 1-10 in the reply filed on February 18, 2026 is acknowledged. Claims 11-20 are withdrawn from further consideration. Information Disclosure Statement The information disclosure statement s (IDS) submitted on February 13, 2024, May 13, 2024, May 30, 2024, September 3, 2024, and October 30, 2024 are in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement s ha ve been considered except as otherwise indicated. The examiner notes that the reference KLAUS, J.W. et. al., “Atomic Layer Deposition of Tungsten Nitride Films Using Sequential Surface Reactions”, Journal of Electrochemical Society, 2000, 8 pages, Volume 147, No 3 has been lined through because this reference is a duplicate of KLAUS, J.W. et. al., “Atomic Layer Deposition of Tungsten Nitride Films Using Sequential Surface Reactions”, Journal of The Electrochemical Society, 2000, pages 1175-1181, Vol. 147, No 3, The Electrochemical Society . Drawings The drawings are objected to because figure 1F does not contain a lead line from the reference number 101C pointing to the memory cell arrangement and figure 1G does not contain a lead line from the reference number 101D pointing to the memory cell arrangement. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “ wherein each memory cell of the plurality of memory cells comprises a memory layer stack a respective three-dimensional structure of the plurality of three-dimensional structures ,” on page 1 lines 10-21. The limitation renders claim 1 indefinite because this limitation does not describe the relationship between a memory layer stack and a respective three-dimensional structure of the plurality of three-dimensional structures. For examination purposes, this limitation will be interpreted as wherein each memory cell of the plurality of memory cells comprises a memory layer stack disposed over a respective three-dimensional structure of the plurality of three-dimensional structures Claims 2-10 are also rejected for containing the same limitation because claims 2-10 depend from claim 1. Claim 1 recites the limitation “its interface to the memory layer stack,” on page 1 lines 19-20. There is insufficient antecedent basis for this limitation in the claim. For examination purpose s , this limitation will be interpreted as an interface to the memory layer stack. Claims 2-10 are also rejected for containing the same limitation because claims 2-10 depend from claim 1. Claim 2 recites the limitation “ wherein the respective three-dimensional structure comprises at least one of a trench, a cup, a nanowire, nanoparticles, or a surface of a porous material ,” on page 2 lines 10-11. This limitation renders claim 2 indefinite because it is unclear how the respective three-dimensional structure can have more than one of the listed structures. For example, it is unclear how the respective three-dimensional structure can be a trench, a nanowire, and a porous material. For examination purposes, this limitation will be interpreted as wherein the respective three-dimensional structure has a structure selected from the group consisting of a trench, a cup, a nanowire, nanoparticles, or a surface of a porous material . Claim 4 recites the limitation “wherein the oxide layer substantially consists of a low-k material,” on page 2 line 20. The term “ low ” is a relative term which renders the claim indefinite. The term “ low ” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The examiner notes it is unclear what numerical value s of dielectric con s tants are consider ed to be low dielectric constants. For examination purpose s , this limitation will be interpreted as wherein the oxide layer substantially consists of a dielectric material having a dielectric constant less than 5 . Claim 5 is also rejected for containing the same limitation because claim 5 depends from claim 4. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1- 2 and 6 -9 are rejected under 35 U.S.C. 103 as being unpatentable ove r Chen et al. (US 2023/0389324) hereinafter Chen ‘324 in view of Leng (US 2022/0399352 ) . Regarding Claim 1: Chen ‘324 discloses a memory cell arrangement, comprising: a substrate (substrate for memory array , See fig. 1, ref. no. 120, fig. 3 B , ref. no. 132, paragraphs 21 , 26-27 , and 3 7 ) comprising a plurality of three-dimensional structures (deep trench es formed in substrate, See fig. 3 B and paragraph 26. The examiner notes that the storage element shown in figure 3B is a representative example of one storage element of one memory cell of the memory array and that the substrate for the memory array will include a plurality of deep trenches because the memory array includes a plurality of memory cells) ; a plurality of memory cells (plurality of 1T1F memory cells, See fig s . 1, 4A, ref. no. 125, paragraph 21 , 23 , 41 ) ; and a plurality of sets of control lines (bit lines , source lines , and word lines for selecting a 1T1F memory cell, See paragraph 23 and 41 ) for selectively addressing one or more memory cells of the plurality of memory cells; wherein each memory cell of the plurality of memory cells comprises a memory layer stack (storage element disposed over the deep trench , See fig. 3 B , ref. no. 128) a respective three-dimensional structure of the plurality of three-dimensional structures, the memory layer stack comprising: a first electrode (bottom electrode, See fig. 3 B , ref. no. 134, paragraphs 27 and 29) ; a memory element (ferroelectric film, See fig. 3 B , ref. no. 140, paragraphs 27 and 32) disposed over the first electrode, the memory element substantially consisting of one or more spontaneously polarizable transition-metal-oxides (hafnium oxide, See paragraph 32) ; and a second electrod e (top electrode, See fig. 3 B , ref. no. 142, paragraphs 27 and 33) disposed over the memory element, wherein the first electrode, the second electrode, and the memory element form a memory capacitor (the bottom electrode, ferroelectric film, and the top electrode form a capacitor structure . See fig. 3B, ref. nos. 134, 140, 142. The examiner also notes that Chen ‘324 discloses storing data based on a first capacitance value and a second capacitance value . See paragraph 26) ; wherein the substrate comprises an oxide layer (dielectric layer of Aluminum Oxide Al 2 O 3 , See fig. 3B, ref. no. 133 and paragraph 37), at its interface to the memory layer stack and wherein the first electrode comprises a first electrically conductive electrode layer substantially consisting of tungsten (the bottom electrode may be formed of tungsten, See paragraph 29) and wherein the second electrode comprises a second electrically conductive electrode layer substantially consisting of tungsten (the top electrode may include tungsten, See paragraph 33) and a second functional layer substantially consisting of a second metal nitride (the top electrode may include conductive metallic nitride, See paragraph 33) or a second metal-oxynitride . Chen does not disclose a first functional layer substantially consisting of a first metal nitride or a first metal-oxynitride, wherein the first electrically conductive electrode layer is disposed between the first functional layer and the memory element and wherein the first electrically conductive electrode layer is disposed in direct contact with the first functional layer; and wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer and wherein the second functional layer is disposed in direct contact with the memory element. Leng discloses a first functional layer substantially consisting of a first metal nitride (glue layer of titanium nitride, See fig. 1A, ref. no. 142 and paragraph 51 ) or a first metal-oxynitride, wherein the first electrically conductive electrode layer (cup-shaped bottom electrode formed from tungsten is disposed between the glue layer of titanium nitride and the cup-shaped ferroelectric element, See fig. 1A, ref. nos. 130, 134, 142 , and paragraphs 50-51 ) is disposed between the first functional layer and the memory element and wherein the first electrically conductive electrode layer is disposed in direct contact with the first functional layer (cup-shaped bottom electrode formed from tungsten is in direct contact with the glue layer of titanium nitride, See fig. 1A, ref. nos. 130, 142, and paragraph 51 ) ; and It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 to include a first functional layer substantially consisting of a first metal nitride or a first metal-oxynitride, wherein the first electrically conductive electrode layer is disposed between the first functional layer and the memory element and wherein the first electrically conductive electrode layer is disposed in direct contact with the first functional layer as taught by Leng in order in improve adhesion between the bottom electrode and the dielectric layer of Aluminum Oxide Al 2 O 3 . The above stated combination of Chen ‘324 and Leng does not disclose wherein the second functional layer is disposed between the memory element and the second electrically conductive electrode layer and wherein the second functional layer is disposed in direct contact with the memory element. Leng discloses a n electrode formed from tungsten directly formed on a glue layer of titanium nitride to improve adhesion of the electrode formed from tungsten and an oxide region (See fig. 1A, ref. nos. 108, 130, 142, and paragraphs 46 and 51 ) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Leng to include the top electrode having a tungsten layer formed directly on a conductive metallic nitride layer as taught by Leng in order in improve adhesion between the top electrode and the ferroelectric film. Regarding Claim 2: Chen ‘324 discloses wherein the respective three-dimensional structure comprises at least one of a trench (deep trenches formed in substrate, See fig. 3B and paragraph 26) , a cup, a nanowire, nanoparticles, or a surface of a porous material. Regarding Claim 6: Chen ‘324 discloses wherein the one or more transition-metal-oxides of the memory element are hafnium oxide (hafnium oxide, See paragraph 32) , zirconium oxide ( zirconium oxide , See paragraph 32) , or hafnium zirconium oxide ( hafnium zirconium oxide , See paragraph 32) . Regarding Claim 7: Chen ‘324 discloses wherein the first metal nitride and/or the second metal nitride is tungsten nitride (the conductive metallic nitride may be tungsten nitride, See paragraph 33) ; and/or wherein the first metal-oxynitride and/or the second metal-oxynitride is tungsten-oxynitride. Regarding Claim 8: Leng discloses wherein the first functional layer and/or the second functional layer has a thickness greater than 1nm (glue layer of titanium nitride may have a thickness in the range of 50-500 angstroms, See paragraph 65 ). Regarding Claim 9: The above stated combination of Chen ‘324 and Leng discloses wherein the first metal nitride (Leng disclose s the glue layer is titanium nitride, See paragraph 51 ) and/or the second metal nitride (Chen ‘324 discloses the conductive metal nitride may titanium nitride, tungsten nitride, or tantalum nitride, See paragraph 33) is one of: titanium nitride, tungsten nitride, molybdenum nitride, tantalum nitride, niobium nitride, hafnium nitride, or zirconium nitride. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable ove r Chen et al. (US 2023/0389324) in view of Leng (US 2022/0399352 ) further in view of Gong et al. (US 2024/0074207) . Regarding Claim 3: The above stated combination of Chen ‘324 and Leng discloses the above stated memory cell arrangement. The above stated combination of Chen ‘324 and Leng further discloses wherein the first electrically conductive electrode conformally covers the first functional layer (the bottom electrode formed from a tungsten layer conformally covers a titanium nitride layer , See Leng fig. 1A, ref. nos. 130, 142 , and paragraph 51 ) and/or wherein the second electrically conductive electrode conformally covers the second functional layer (the top electrode formed from a tungsten layer conformally covers a titanium nitride layer, See Leng fig. 1A, ref. nos. 130, 142 , and paragraph 51 ) ; and wherein the respective three-dimensional structure has an aspect ratio equal to or greater than six (the aspect ratio of the deep trench ranges from about 5 to about 30, See Chen ‘324 paragraph 27) . The above stated combination of Chen ‘324 and Leng does not disclose wherein the respective three-dimensional structure has a width equal to or less than 200nm . Gong discloses a ferroelectric ra ndom-access memory cell having a width between 10-1000nm (See fig. 10, ref. no. 122 and paragraph 66). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Leng to include the respective three-dimensional structure has a width equal to or less than 200nm as taught by Gong in order increase memory density of the memory array by reducing the width of the storage elements. Claim 4-5 are rejected under 35 U.S.C. 103 as being unpatentable ove r Chen ‘324 et al. (US 2023/0389324) in view of Leng (US 2022/0399352 ) further in view of Chen et al. (US 2021/0035992) hereafter Chen ‘992 . Regarding Claim 4: The above stated combination of Chen ‘324 and Leng discloses the above stated memory cell arrangement. The examiner notes th at Chen ‘ 324 discloses an inter-layer dielectric formed from silicon dioxide deposited over the top electrode of the storage element. (See fig. 3B, ref. no. 156 and paragraph 34). The above stated combination of Chen ‘324 and Leng does not disclose wherein the oxide layer substantially consists of a low-k material. Chen ‘992 discloses a lower insulating structure formed from silicon dioxide formed around a bottom electrode of tungsten and titanium nitride of a FeRam device (See fig. 2A, ref. no. 110, and paragraphs 25, 28, and 32). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory cell arrangement of Chen ‘324 and Leng to replace the dielectric layer of Aluminum Oxide Al 2 O 3 with a dielectric layer of silicon dioxide as taught by Chen in order to simply fabrication of the memory array by reducing the number of different material used for fabrication. Regarding Claim 5: Chen discloses wherein the respective three-dimensional structure is a trench disposed within the oxide layer or wherein the respective three-dimensional structure is a trench disposed within the substrate and conformally covered with one or more oxide layers (the deep trench in the substrate is conformally covered by the dielectric layer. See Chen ‘324 fig. 3B, ref. nos. 132, 133 and paragraph 37) . Allowable Subject Matter Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the disclosure of Chen ‘324 and Leng as discussed above fail to teach or suggest the limitations of claim 10 because Chen does not teach the bottom electrode further comprises a further first functional layer substantially consisting of the first metal nitride or the first metal-oxynitride, wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer; or the top electrode further comprises a further second functional layer substantially consisting of the second metal nitride or the second metal-oxynitride, wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer. Leng also does not disclose the bottom electrode further comprises a further first functional layer substantially consisting of the first metal nitride or the first metal-oxynitride, wherein the further first functional layer is disposed between and in direct contact with the memory element and the first electrically conductive electrode layer; or the top electrode further comprises a further second functional layer substantially consisting of the second metal nitride or the second metal-oxynitride, wherein the further second functional layer is disposed directly on the second electrically conductive electrode layer. Additionally, the prior art also fails to provide other relevant disclosures which are properly combinable with Chen ‘324 and/or Leng to teach or suggest the limitations of claim 10. Therefore, claim 10 includes allowable subject matter. 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