Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 13-19 and 28-33 in the reply filed on February 23, 2026 is acknowledged. Claims 20-26 are withdrawn from further consideration.
Information Disclosure Statement
The information disclosure statements (IDS)s submitted on October 13, 2023 and November 30, 2023 were filed before the mailing of a first Office action on the merits. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a vertical semiconductor component including a transistor,” recited in claim 13 on page 2 line 8 must be shown or the feature(s) canceled from the claim(s). The examiner notes that a transistor is not shown in the figures because the portions of the transistors shown in the figures require a drain to form a transistor and none of the figures show a drain. Additionally, “a substrate and an intermediate layer are absent from at least a portion of the semiconductor component such that the contact semiconductor layer is exposed on a side opposite the measuring electrode,” recited in claim 30 on page 4 lines 23-26 must be shown or the feature(s) canceled from the claim(s). Further, “a drain electrode disposed on the contact semiconductor layer on a side opposite the measuring electrode,” recited in claim 32 on page 5 lines 2-3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “100” has been used to designate two structurally different transistors, one in figure 1 and another in figures 3-4. Additionally, the drawing are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “113” has been used to designate four measuring electrodes having different locations and/or shapes in figures 1-4. Further, the drawing are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “114” has been used to designate two transition regions having different shapes in figures 3-4. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: the specification uses the same reference character to refer to different elements. The specification recites “drain electrode 106,” on page 12 lines 16, reference character 106 is understood to refer to the gate electrode. Appropriate correction is required.
The disclosure is objected to because of the following informalities: the specification refers to two structurally different transistors as the same transistor. The specification recites “In Fig. 2, in a plan view which is substantially perpendicular to the sectional view of Fig. 1, the arrangement and design of the measuring electrode 113 is again shown,” on page 12 lines 18-19. The examiner notes that transistors shown in figures 1 and 2 are structurally different. The examiner first notes that a transistor having a layout of a gate electrode 106, a source electrode 107, and a measuring electrode 113 as shown in figure 2 does not have a cross section that includes all three of the gate electrode 106, the source electrode 107, and the measuring electrode 113 as shown in figure 1 and further does not have a cross section where the source electrode 107 is located to the left of the gate electrode 106 as shown in figure 1. The examiner also notes that figure 1 shows the gate electrode 106 and the measuring electrode 113 moved back from the edge of the transistor, while figure 2 shows the gate electrode 106 and the measuring electrode 113 at the edge of the transistor. Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 28 and 33 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 28 recites the limitation “wherein the semiconductor component comprises a recess extending from a front side of the semiconductor component through the drift layer and/or the active layer to expose a contact semiconductor layer, and wherein the measuring electrode is disposed directly on the exposed contact semiconductor layer within the recess,” on page 4 lines 13-17. This limitation introduces new matter because the specification does not disclose extending from a front side of the semiconductor component through the drift layer and/or the active layer to expose a contact semiconductor layer.
Claim 33 recites the limitation “the semiconductor component includes a recess extending from a front side of the semiconductor component to the contact semiconductor layer, the measuring electrode being disposed directly on the contact semiconductor layer within the recess,” on page 5 lines 9-11. This limitation introduces new matter because the specification does not disclose a recess extending from a front side of the semiconductor component to the contact semiconductor layer.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16-17 and 30-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 16 recites “a foreign substrate,” on page 2 line 22 and claim 17 recites “a foreign substate,” on page 2 line 26. This limitation renders claims 16 and 17 indefinite because it is unclear how the term foreign further define the structure of the substrate. For example, the term foreign may refer to a place of manufacture for the substrate. For examination purposes, a foreign substrate will be interpretated as a substrate.
Claim 30 recites “the contact semiconductor layer,” on page 4 line 26, claim 31 recites “the contact semiconductor layer,” on page 4 line 30, and claim 32 recites “the contact semiconductor layer,” on page 5 line 2, there is insufficient antecedent basis for these limitations in the claims. For examination purposes, claims 30-32 will be treated as depending from dependent claim 15 instead of independent claim 13.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-18, 28-29, 31, and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyamoto et al. (US 2012/0199889).
Regarding Claim 13:
Miyamoto discloses a vertical semiconductor component including transistor, comprising:
a drift layer (n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. no. 23 and paragraph 66) and/or an active layer (p-type Gallium Nitride layer, See fig. 1A, ref. no. 24 and paragraph 66. The examiner noted that the p-type Gallium Nitride layer is an active layer because a channel is formed in the p-type Gallium Nitride layer when the vertical field effect transistor is turn on.) formed using gallium nitride (GaN); and
at least two electrodes (source electrodes, drain electrodes, and gate electrode, See fig. 1A, ref. nos. 12, 13, 14 and paragraph 66) including at least one measuring electrode (the right drain electrode, See fig. 1A ref. no. 13. The examiner notes that the drain electrode can be used for measuring purposes such as measuring current flowing into or out of the drain electrode.), the measuring electrode being formed at a lower vertical level than at least one other of the electrodes (the right drain electrode is located at a lower vertical level than the source electrodes and the gate electrode, See fig. 1A, ref. no. 12, 13, 14) and is configured to be contactable from vertically above (the right drain electrode has a top surface, thus, the drain electrode is configured to be contactable from vertically above, See fig. 1A, ref. no. 13).
Regarding Claim 14:
Miyamoto discloses wherein the at least two electrodes includes three electrodes (two source electrode, two drain electrode, and one gate electrode for a total of five electrodes, See fig. 1A, ref. nos. 12, 13, 14).
Regarding Claim 15:
Miyamoto discloses wherein the measuring electrode is formed on a contact semiconductor layer (the drain electrodes are formed on high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. nos. 13, 22, and paragraph 66).
Regarding Claim 16:
Miyamoto discloses a foreign substrate (sapphire substrate, See fig. 1A, ref. no. 1 and paragraph 66) which does not include gallium nitride.
Regarding Claim 17:
Miyamoto an intermediate layer (buffer layers, See fig. 1A, ref. no. 20, 21 and paragraph 66) configured to compensate for a lattice mismatch between a foreign substrate (sapphire substrate, See fig. 1A, ref. no. 1 and paragraph 66) and the contact semiconductor layer (high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. no. 22, and paragraph 66) and/or the drift layer.
Regarding Claim 18:
Miyamoto discloses wherein the measuring electrode extends over a portion of a width and of a length of the semiconductor component (width and length of the drain electrodes over the high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. nos. 13, 22, The examiner notes that the vertical transistor shown in figure 1A is a three dimensional structure, thus, the drain electrode have width, length, and height dimensions.) and is arranged in an edge region of the semiconductor component (the drain electrodes are arranged on the edges of high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. nos. 13, 22, and paragraph 66).
Regarding Claim 28:
Miyamoto discloses wherein the semiconductor component comprises a recess extending from a front side of the semiconductor component through the drift layer and/or the active layer to expose a contact semiconductor layer (the right drain electrode is uncovered in the vertical direction, See fig. 1A, ref. no. 13), and wherein the measuring electrode is disposed directly on the exposed contact semiconductor layer within the recess (the right drain electrodes is disposed directly the high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. nos. 13, 22).
Regarding Claim 29:
Miyamoto discloses wherein the semiconductor component is free of a carrier material attached to a front side of the semiconductor component (the front side of the vertical transistor is not attached to carrier, See fig. 1A), such that the measuring electrode and at least one further electrode are simultaneously contactable from vertically above (the source electrodes, the drain electrodes, and the gate electrode are uncovered in the vertical direction, See fig. 1A, ref. no. 12, 13, 14).
Regarding Claim 31:
Miyamoto discloses wherein no drain electrode is disposed on the contact semiconductor layer on a side opposite the measuring electrode (there are no drain electrodes are located below the high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. nos. 13, 22, and paragraph 66).
Regarding Claim 33:
Miyamoto discloses the vertical semiconductor component further comprises a substrate (sapphire substrate, See fig. 1A, ref. no. 1 and paragraph 66);
a contact semiconductor layer (the high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. no. 22, and paragraph 66) is disposed between the substrate and the drift layer and/or the active layer; and
the semiconductor component includes a recess extending from a front side of the semiconductor component to the contact semiconductor layer (a portion of the high concentration n-type Aluminum Gallium Nitride layer is uncovered in the vertical direction, See fig. 1A, ref. no. 22), the measuring electrode being disposed directly on the contact semiconductor layer within the recess (the right drain electrodes is disposed directly the high concentration n-type Aluminum Gallium Nitride layer, See fig. 1A, ref. nos. 13, 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-16, 18-19, 29, and 32 rejected under 35 U.S.C. 103 as being unpatentable over Yoshimura (JP H07245401 A) in view of Motonobu et al. (US 2015/0014699). The examiner notes that the citations to paragraphs in Yoshimura refer to paragraphs in the attached English language translation of Yoshimura.
Regarding Claim 13:
Yoshimura discloses a vertical semiconductor component including a transistor, comprising:
a drift layer (N- epitaxial layer, See fig. 1, ref. no. 8 and paragraph 11) and/or an active layer; and
at least two electrodes (drain electrode, source electrode, gate electrode, and detection electrode, See fig. 1, ref. nos. C1, 4, 5, 6, fig. 3, ref. nos. 3, 4, 5, 6, and paragraphs 10-11) including at least one measuring electrode (detection electrode, See figs. 1, 3, ref. no. 6 and paragraph 10) the measuring electrode being formed at a lower vertical level than at least one other of the electrodes (the detection electrode is formed at a lower vertical level than the gate electrode because the aluminum metal film for the detection electrode is formed on the N- epitaxial layer while the aluminum metal film for the gate electrode is formed on a phosphorus-doped polysilicon film and a silicon dioxide file, See fig. 1, ref. nos. 5, 6, 10a, 13, and paragraph 11) and is configured to be contactable from vertically above (the detection electrode has a top surface, thus, the detection electrode is configured to be contactable from vertically above, See figs. 1, 3, ref. no. 6).
Yoshimura does not disclose the drift layer is formed using gallium nitride (GaN).
Motonobu discloses a drift layer is formed using gallium nitride (GaN) (drift layer maybe an N-type GaN layer, See fig. 5, ref. no. 408 and paragraph 35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical semiconductor component including a transistor of Yoshimura to include the drift layer is formed using gallium nitride (GaN) as taught by Motonobu in order to improve transistor performance as compared to conventional silicon transistors. (See Motonobu paragraph 5)
Further, the examiner notes that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the drift layer using gallium nitride (GaN) since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding Claim 14:
Yoshimura discloses wherein the at least two electrodes includes three electrodes (drain electrode, source electrode, gate electrode, and detection electrode, See fig. 1, ref. nos. C1, 4, 5, 6, fig. 3, ref. nos. 3, 4, 5, 6, and paragraphs 10-11 for a total of four electrodes).
Regarding Claim 15:
Yoshimura discloses wherein the measuring electrode is formed on a contact semiconductor layer (N+ diffusion region, See fig. 1, ref. no. 15, and paragraph 11).
Regarding Claim 16:
Yoshimura discloses a foreign substrate (silicon substrate, See fig. 1, ref. no. 9 and paragraph 11) which does not include gallium nitride.
Regarding Claim 18:
Yoshimura discloses wherein the measuring electrode extends over a portion of a width and of a length of the semiconductor component (width and length of the detection electrode extend over the N- epitaxial layer, See fig. 1, ref. nos. 6, 8, and fig. 3, ref. no. 6) and is arranged in an edge region of the semiconductor component (the detection electrode is arranged in an edge region of vertical DMOS transistor, See fig. 3, ref. no. 6).
Regarding Claim 19:
Yoshimura wherein the edge region is a corner region of the semiconductor component (the detection electrode is arranged in a corner region of vertical DMOS transistor, See fig. 3, ref. no. 6).
Regarding Claim 29:
Yoshimura discloses wherein the semiconductor component is free of a carrier material attached to a front side of the semiconductor component (the front side of the vertical DMOS transistor is not attached to carrier, See fig. 1), such that the measuring electrode and at least one further electrode are simultaneously contactable from vertically above (the detection electrode, the source electrode, and the gate electrode are uncovered in the vertical direction, See figs. 1, 3, ref. no. 4, 5, 6).
Regarding Claim 32:
Yoshimura discloses a drain electrode (drain electrode, See fig. 1, ref. no. C1, fig. 3, ref. no. 3, and paragraphs 10-11) disposed on the contact semiconductor layer on a side opposite the measuring electrode (the drain electrode is disposed on the N+ diffusion region through the silicon substrate and the N- Epitaxial layer, See fig. 1, ref. nos. 8 and 9).
Claims 13-16 and 29-32 are rejected under 35 U.S.C. 103 as being unpatentable over Motonobu et al. (US 2015/0060943) in view of Ren et al. (CN 110739350 A). The examiner notes that the citations to paragraphs in Ren refer to paragraphs in the attached English language translation of Ren.
Regarding Claim 13:
Motonobu discloses a vertical semiconductor component including transistor, comprising:
a drift layer (first GaN semiconductor layer, See figs. 12-14, ref. no. 305, paragraphs 62 and 66) and/or an active layer (second GaN semiconductor layer, See fig. 12-14, ref. no. 320 and paragraph 66. The examiner noted that the second GaN semiconductor is an active layer because a channel is formed in the second GaN semiconductor when the nitride-based transistor is turn on.) formed using gallium nitride (GaN layers, See paragraph 66); and
at least two electrodes (source electrodes and gate electrode, See fig. 12-14, ref. nos. 374, 380, paragraphs 62 and 75-77).
Motonobu does not disclose at least one measuring electrode, the measuring electrode being formed at a lower vertical level than at least one other of the electrodes and is configured to be contactable from vertically above.
Ren discloses including at least one measuring electrode (detection electrode, See figs. 1, ref. no. 190 and paragraphs 54-55) the measuring electrode being formed at a lower vertical level than at least one other of the electrodes (the detection electrode is formed at a lower vertical level than the source electrode and gate electrode, See fig. 1, ref. nos. 180, 190.) and is configured to be contactable from vertically above (the detection electrode has a top surface and is formed in through hole, thus, the detection electrode is configured to be contactable from vertically above, See figs. 1, ref. nos. 190, 200 and paragraphs 54-55).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical semiconductor component including a transistor of Motonobu to include at least one measuring electrode, the measuring electrode being formed at a lower vertical level than at least one other of the electrodes and is configured to be contactable from vertically above as taught by Ren in order to test the operating characteristics of the nitride-based transistor. (See Ren paragraph 31)
Regarding Claim 14:
The above stated combination of Motonobu and Ren discloses wherein the at least two electrodes includes three electrodes (source electrode and gate electrode, See Motonobu fig. 12, ref. nos. 374, 380, and paragraph 75-77 and detection electrode, See Ren figs. 1, ref. no. 190 and paragraphs 54-55 for a total of three electrodes).
Regarding Claim 15:
The above stated combination of Motonobu and Ren discloses wherein the measuring electrode is formed on a contact semiconductor layer (heavily doped nitride-based semiconductor layer, See Motonobu figs. 12-14, ref. no. 302 and paragraphs 62-63. The examiner notes that Ren discloses the detection electrode can be formed at any functional level. See paragraph 31.).
Regarding Claim 16:
Motonobu discloses a foreign substrate (sapphire substrate, See fig. 12, ref. no. 301 and paragraph 64) which does not include gallium nitride.
Regarding Claim 29:
The combination of Motonobu and Ren discloses wherein the semiconductor component is free of a carrier material attached to a front side of the semiconductor component (the front side of the nitride-based transistor is not attached to carrier, See figs. 12-14), such that the measuring electrode and at least one further electrode are simultaneously contactable from vertically above (Motonobu discloses the inclusion of the heat sink is optional, thus, in the option where the heat sink is not included the source electrode, See Motonobu figs. 12, ref. no. 380 and paragraph 78, and the detection electrode, See Ren figs. 1, ref. nos. 190, 200, are simultaneously contactable from vertically above).
Regarding Claim 30:
Motonobu discloses wherein a substrate (a substate is not present in the nitride-based transistor structure shown in figure 14, See fig. 14 and paragraph 79) and an intermediate layer (the examiner notes that in an apparatus claim the absence of a layer does not require the layer to be present in the apparatus and then later removed, but rather only requires the layer not be present in the apparatus. For example, a layer that is not deposited during fabrication of an apparatus would be absent from the apparatus. In the present case, no layer is being read on an intermediate layer, so an intermediate layer is absent from the nitride-based transistor.) are absent from at least a portion of the semiconductor component such that the contact semiconductor layer is exposed on a side opposite the measuring electrode (the heavily doped nitride-based semiconductor layer is exposed on the bottom side, See Motonobu figs. 14, ref. no. 302 and paragraph 79).
Regarding Claim 31:
Motonobu disclose no drain electrode is disposed on the contact semiconductor layer on a side opposite the measuring electrode (no drain electrode is disposed on the heavily doped nitride-based semiconductor layer, See fig. 13, ref. no. 302 and paragraph 80).
Regarding Claim 32:
Motonobu disclose a drain electrode disposed on the contact semiconductor layer on a side opposite the measuring electrode (drain electrode, See fig. 14, ref. no. 390 and paragraph 80).
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899