DETAILED ACTION
This action is responsive to the election received on 03/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in the European Patent Office on 10/25/2022.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 10/13/2023 has/have been considered by the examiner and made of record in the application file.
Election/Restrictions
Applicant's election with traverse of Species A (Figures 1-10) in the reply filed on 03/13/2026 is acknowledged. The traversal is on the ground(s) that a search for all of the pending claims can be made without serious burden. The examiner respectfully disagrees. This is not found persuasive because there are clear mutually exclusive features for each of the respective identified species, elaborated in both the specification and claims, which were identified in the requirement for restriction mailed on 03/03/2026. Applicant has not submitted or identified evidence to show the identified species to be obvious variants or stated on the record that they are obvious variants. The requirement is still deemed proper and is therefore made FINAL.
Claim(s) 7-11 and 13 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/13/2026. Claims 9-11 and 13 were withdrawn from consideration by the applicant in the above identified response. Claims 7-8 are further interpreted by the examiner to read on a non-elected species. In particular, claim 7 requires “removing the first temporary process layer subsequent to forming the metal via”. This limitation is disclosed in [00107] of the instant application in relation to Figure 18, such that both the via hole and the via opening may be filled by the metal via which then extends above the source/drain body (as required in claim 8). These two claims are therefore drawn to non-elected species D, identified in the restriction requirement as being directed to Figures 18-19, and are withdrawn from consideration.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "removing the first temporary process layer prior to forming the metal via" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. None of the claims on which claim 6 depends (claims 1 and 5) have recited “a first temporary process layer” to provide proper antecedent basis. However, claim 2 does recite “a first temporary process layer”. Therefore, it is unclear if claim 6 should depend on claim 2 such that it requires all the limitations of claim 2, or if claim 6 should read as "removing a first temporary process layer prior to forming the metal via". Therefore, claim 6 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention. For the purposes of this examination, claim 6 will be interpreted to read as "removing [[the]] a first temporary process layer prior to forming the metal via"
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, 6, 12, and 14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0105614 A1; Xie et al.; 03/2024; (“Xie”).
Regarding Claim 1. Xie discloses A method for interconnecting a buried wiring line and a source/drain body (Figures 1-14, [0072]-[0104], method of fabrication), the method comprising:
forming a fin structure (#109, Figures 1 to 2, FET stacks shaped like fins) on a substrate (#102, Figure 2B, substrate which #109s are on), the fin structure comprising at least one channel layer (#108, Figure 2B, nanosheet channel layer);
forming a buried wiring line (#126, Figures 4 to 5, lower portion VBPR (via-to-backside power rail)) in a trench (#124, Figures 4 to 5, opening) extending alongside the fin structure (Figure 4, #124s extend alongside the FET stacks), wherein the buried wiring line is capped by a first insulating layer structure (#128, Figures 5 to 6, self-aligned dielectric spacer that at least partially caps #126);
forming a source/drain body (#114a/b, Figures 2 to 3, source/drain regions) on the at least one channel layer (Figure 3B, #114a/b is formed on #108s) by epitaxy ([0082], “source/drain regions 114a and 114b may be formed using epitaxial growth processes”);
forming a via hole in the first insulating layer structure (#124, Figure 6C, opening that remains in #128) to expose an upper surface of the buried wiring line (Figure 6C, #124 in #128 exposes an upper surface of #126);
forming a metal via in the via hole (#130, Figures 6 to 7, middle portion VBPR);
forming a second insulating layer structure (#132 and #134, Figures 7 to 9, ILD layer and mask layer) over the first insulating layer structure (Figures 8 and 9, the combination of #132 and #134 is over a top and side surface of #128), wherein a contact opening is defined in the second insulating layer structure (#136, Figure 9D, top portion VBPR opening) to expose the source/drain body and an upper via portion of the metal via (Figure 9D, #136 exposes a sidewall of #114a/b and a sidewall of an upper portion of #130); and
forming a source/drain contact (#144 and #145, Figure 10E, middle-of-the-line contact and top portion VBPR) in the contact opening (Figures 9 to 10, #144 and #145 are formed in the opening), on the upper via portion and the source/drain body (Figure 10E, #144 and #145 is on the upper portion of #130 and on #114a/b), thereby interconnecting the buried wiring line and the source/drain body (Figure 10E, #114a/b is electrically connected to #126 through #145).
Regarding Claim 5. Xie discloses The method according to claim 1, wherein the metal via (#130) is formed by selective deposition of metal in the via hole in the first insulating layer structure ([0091], “form a first and a second middle portion VBPR 130 (collectively, middle portion VBPR 130). The conductive metal is deposited by conventional deposition processes such as PVD, ALD, CVD, and/or plating. Alternatively, it can be a bottom up selective metal growth process from the lower portion VBPR 126”, i.e. #130 may be formed by selective metal growth/deposition in the via hole where #126 is located).
Regarding Claim 6. Xie discloses The method according to claim 5, further comprising removing [[the]] a first temporary process layer (#122, Figures 4 to 5, mask layer which is removed by etching according to [0089]) prior to forming the metal via (Figures 4 to 7, #122 is removed in Figures 4 to 5 prior to forming #130 in Figures 6 to 7).
Regarding Claim 12. Xie discloses The method according to claim 1, wherein the second insulating layer structure (#132 and #134) is formed to cover the upper via portion (Figure 9B, #132 covers the upper portion of #130) and the source/drain body (Figures 9A and 9D, #134 and #132 at least partially cover #114a/b), and wherein the contact opening is formed by etching the second insulating layer structure ([0093], #136 is formed by selective etching of #134 and #132) to expose the source/drain body and the upper via portion (Figure 9D, #136 exposes a sidewall of #114a/b and a sidewall of an upper portion of #130).
Regarding Claim 14. Xie discloses The method according to claim 1, wherein the buried wiring line is a buried power rail (BPR) ([0089], [0104], Figure 14D, #126 is a via directly electrically connected to buried power rail #152 such that it may function as a buried power rail).
Claim(s) 1, 4, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0373331 A1; Kim et al.; 11/2020; (“Kim”).
Regarding Claim 1. Kim discloses A method for interconnecting a buried wiring line and a source/drain body (Figures 2A to 19D, [0010], method of manufacturing an integrated circuit device), the method comprising:
forming a fin structure (#F2, Figure 2B, fin-type active area) on a substrate (#100, Figure 2B substrate which #F2 are on), the fin structure comprising at least one channel layer ([0022], “channels are formed on the upper surface and opposite side walls of each fin-type active area”);
forming a buried wiring line (#150, Figure 8A, buried rail) in a trench (#BRH, Figure 8A, buried rail hole) extending alongside the fin structure (Figure 6A, #BRH extends alongside #F2), wherein the buried wiring line is capped by a first insulating layer structure (#112c, Figure 16, cover insulation layer capping #150);
forming a source/drain body (#130, Figure 18, source/drain regions) on the at least one channel layer by epitaxy (Figure 18 and [0026], #130s are formed on the sidewalls of the fins which are the channel regions as described above and may be formed by epitaxial growth);
forming a via hole (#VH, Figure 19B, via hole which extends through #112c) in the first insulating layer structure to expose an upper surface of the buried wiring line (Figure 19B, #VH exposes the upper surface of #150);
forming a metal via in the via hole (#VC, Figure 19B, via contact formed in #VH);
forming a second insulating layer structure (#126, Figure 19B, inter-gate insulation layer) over the first insulating layer structure (Figure 19B, #126 is formed over #112c), wherein a contact opening (#CH1, Figure 19B, first contact hole) is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via (Figure 19B, #CH1 is formed in #126 and exposes upper surfaces of both #130 and #VC); and
forming a source/drain contact (#CP1, Figure 19B, conductive plug which contacts #130) in the contact opening (Figure 19B, #CP1 is formed in #CH1), on the upper via portion and the source/drain body, thereby interconnecting the buried wiring line and the source/drain body (Figure 19B, #CP1 is formed on the upper portions of both #130 and #VC such that #130 and #150 are electrically interconnected).
Regarding Claim 4. Kim discloses The method according to claim 1, wherein the upper via portion of the metal via protrudes above the via hole in the first insulating layer structure (Figure 19B, the upper portion of #VC protrudes above the #VH that is in #112c).
Regarding Claim 14. The method according to claim 1, wherein the buried wiring line is a buried power rail (BPR) ([0032], #150 is a buried rail which is part of a buried power delivery structure).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0105614 A1; Xie et al.; 03/2024; (“Xie”) as applied to claim 1 above, and further in view of US 2023/0032866 A1; Wei et al.; 02/2023; (“Wei”).
Regarding Claim 2. Xie discloses The method according to claim 1.
Xie does not disclose forming a first temporary process layer over the first insulating layer structure and the source/drain body; and forming a via opening in the first temporary process layer by etching; wherein the via hole in the first insulating layer structure subsequently is formed by transferring the via opening into the first insulating layer structure by etching, and wherein the first temporary process layer is removed prior to forming the second insulating layer structure. However, Xie teaches that the first insulating layer (#128) is formed by conventional deposition processes in [0090] and teaches the use of masks to form via holes which are then extended into the underlying layers followed by removal of the mask before further processing (see #122 in [0086]-[0089] and Figures 4-5).
Wei teaches the formation of a buried power rail connection to a source/drain (Figures 2-19b) which includes forming a temporary process layer (#137, Figure 17, mask) over the first insulating layer structure (#104, Figures 16-17), which caps a buried wiring line (#111, Figure 16, BPR or buried power rail), and over the source/drain body (#117/#119, Figure 17, source/drain regions); and forming a via opening in the first temporary process layer by etching (Figure 17 and [0043], the mask #137 is patterned/etched to form a via trench); wherein the via hole in the first insulating layer structure subsequently is formed by transferring the via opening into the first insulating layer structure by etching (Figure 17 and [0043], the mask #137 opening is extended into the first insulating layer #104), and wherein the first temporary process layer is removed prior to forming the second insulating layer structure ([0044] and Figure 18, the mask #137 is removed prior to even forming the conductive material in the via hole such that it would necessarily be removed before any subsequent insulating layer structures).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing a temporary mask structure to form a via opening in and extending the opening into underlying insulating structures to form via holes, as was done in Wei, in the method of Xie, since masks may provide protection to prevent the etching of neighboring structures through etch selectivity, preventing damage during subsequent etching steps (see [0026] of Wei)
Regarding Claim 3. Xie in view of Wei disclose The method according to claim 2, wherein the first temporary process layer is an organic material layer (Wei, [0043], #137 may be a carbon based hard mask; Xie, [0086], mask layers may be made of a flowable organic material such as spin-on-carbon).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2025/0359320 A1; Sarkar et al.; 11/2025 – Figures 2 through 18 disclose a method of forming a plurality of intermediate via structures to provide interconnection between buried power rails (#150) and corresponding source drain regions (#130/#140) of fin structures. However, the effective filing date is later than that of the instant application.
US 2025/0285975 A1; Zhou et al.; 09/2025 – Figures 1 through 27C disclose a method of forming a plurality of intermediate via structures (#92a, #96, and #394) to provide interconnection between a buried power rail (#396) and corresponding source drain regions (#28) of fin structures. However, the effective filing date is later than that of the instant application.
US 2024/0105554 A1; Li et al.; 03/2024 – Figures 1 through 15C disclose a method of forming a plurality of intermediate via structures (#156, #134, and #149) to provide interconnection between a buried power rail (#158) and corresponding source drain regions (#124) of fin structures.
US 11,664,374 B2; Chung et al.; 05/2023 – Figures 1 through 31 disclose a method of forming a plurality of intermediate via structures (#112 and #36) to provide interconnection between a buried power rail structure (#166) and corresponding source drain regions (#92) of fin structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE KIM can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TYLER J WIEGAND/Examiner, Art Unit 2812
Prosecution Insights