DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions.
Applicant’s election of claims 1-11 in the reply filed on 2/3/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected method claims, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (20230260977)
Regarding Claim 1, in Fig 12, (and Fig 8) (and paragraph 0041) Chen et al. discloses a semiconductor device comprising: a power delivery network layer 130A/130B; an insulating layer 142 (see Fig. 8) disposed on the power delivery network layer 130A/130B (see paragraph 0041) and having an opening (the spacing/opening/gap between the elements 126 and between through vias 136, see paragraph 0037) therein; a semiconductor layer 124 (see paragraph 0037) filling the opening (the spacing/opening/gap between the elements 126 and between through vias 136, see paragraph 0037) and covering the insulating layer 142 (when looked from the bottom direction); a first through-via 136 (third through via from the right sidewall of 124) extending through the semiconductor layer 124 and electrically connected to the power delivery network layer 130A/130B; a second through-via 136 (second one from the right sidewall of 124) extending through the insulating layer 142 and the semiconductor layer 124 and electrically connected to the power delivery network layer 130A/130B (see Fig. 12 and paragraph 0041); a logic element 126 (for example a transistor as discussed in paragraph 0037) on the semiconductor layer 124 and electrically connected to the first through-via 136 (second one from the right sidewall of 124) ; and a passive element, trench capacitors 128, on the semiconductor layer 124 and electrically connected to the second through-via 136 (second one from the right sidewall of 124) (see paragraphs 0037 and 0038).
Regarding Claim 2, in paragraph 0012, a signal wiring layer i.e. RDL 110 or RDL 106, electrically connected to the logic element 126 (i.e. transistors see paragraph 0037) and the passive element (i.e. trench capacitors 128, see paragraph 0037), wherein the signal wiring layer 106 is on a side of the logic element 126 and the passive element 128 opposite the first through-via and the second through-via.
Regarding Claim 3, the semiconductor layer 124 includes silicon (see paragraph 0037), and the insulating layer 142 includes silicon oxide (see paragraph 0042)
Regarding Claim 4, the logic element 126 (i.e. transistor) includes: a semiconductor substrate (see paragraph 0037); an active pattern disposed on the semiconductor substrate (see paragraph 0037); a power rail, i.e. 130A connected to the first through-via 136 and having a portion in the semiconductor substrate; and a contact electrically connecting the power rail and the active pattern to each other (see paragraph 0037, lines 10-23).
Regarding Claim 5, a lower surface of the insulating layer 142 and a lower surface of the semiconductor layer 124 are coplanar with each other (please note that with respect to lower surface, this has not been tied to any specific orientation and hence examiner can take “flipped” and/or regular orientations of elements 142 and 124 to arrive at the coplanar limitations)
Regarding Claim 6, the first through-via includes 136 (specifically the third one from the right sidewall of element 124) a material different from a material of the second through-via 136 (specifically the second through via from the right sidewall of element 124)(also see paragraph 0038)
Regarding Claim 7, a maximum width of the first through-via 136 (specifically the third one from the right sidewall of element 124) is different from a maximum width of the second through-via (specifically the second through via from the right sidewall of element 124 (see also paragraph 0053. Please also note that “width” limitation is not tied to a specific orientation)
Regarding Claim 8, the maximum width of the first through-via is smaller than the maximum width of the second through-via. (again, the “width” limitation is not tied to any geometrical portion of “through-via” and hence examiner can take any geometrical relationship to arrive at this limitation. Please also see paragraph 0053).
Regarding Claim 9, in Fig 12, (and Fig 8) (and paragraph 0041) Chen et al. discloses a semiconductor device comprising: a substrate layer 124 including an insulating layer 142 (see Fig. 8) and a semiconductor layer 124, wherein the substrate layer includes: a first area (left half portion of the Figure 12) including the semiconductor layer 124; and a second area (right half of the Figure 12) different from the first area and including a stack of the insulating layer142 and the semiconductor layer 124; a logic element 126 (transistor, see paragraphs 0037 and 0053) and a passive element 128 (trench capacitors, see paragraphs 0037 and 0053) on a first (upper/top) surface of the substrate layer 124, wherein the logic element 126 is disposed on the first area (left half portion) of the substrate layer 124 and the passive element 128 is disposed on the second area (the right half portion) of the substrate layer 124; a signal wiring layer 130B on the first (top or upper) surface of the substrate layer 124 and electrically connected to the logic element and the passive element (see paragraphs 0037 and 0041); and a power delivery network layer 130A on a second (lower or bottom) surface of the substrate layer 124 opposite to the first surface.
Regarding Claim 10, a first through-via 136 (specifically the third one from the right sidewall of element 124) extending through the semiconductor layer of the first area and electrically connected to the power delivery network layer and the logic element 126 (see paragraphs 0037, 0041); and a second through-via 136 (the second on from the right sidewall of element 124) extending through the stack of the second area (right half portion of 124) and electrically connected to the power delivery network 130B layer and the passive element 128 (see paragraph 0037 and 0041)
Regarding Claim 11, the logic element 126 includes: a semiconductor substrate; an active pattern on the semiconductor substrate; a power rail connected to the first through-via and having a portion in the semiconductor substrate (paragraph 0037); and a contact electrically connecting the power rail and the active pattern to each other (see paragraph 0037, lines 10-23).
Cited Pertinent Prior Art
Examiner is including Lee et al. (2022/0165721) and Kim et al. (20230260893) as pertinent prior arts that are not relied upon but that do disclose integration of active and passive devices and the power network that electrically connects to integrated active and passive devices
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/ Primary Examiner, Art Unit 2812
2/20/2026