DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (20230260977) in view of Yeh et al. (20220320075).
Regarding Claim 1, in Fig 12, (and Fig 8) (and paragraph 0041) Chen et al. discloses a semiconductor device comprising: a power delivery network layer 130A/130B; an insulating layer 142 (see Fig. 8) disposed on the power delivery network layer 130A/130B (see paragraph 0041) and having an opening (the spacing/opening/gap between the elements 126 and between through vias 136, see paragraph 0037) therein; a semiconductor layer 124 (see paragraph 0037) filling the opening (the spacing/opening/gap between the elements 126 and between through vias 136, see paragraph 0037) and covering the insulating layer 142 (when looked from the bottom direction); a first through-via 136 (third through via from the right sidewall of 124) extending through the semiconductor layer 124 and electrically connected to the power delivery network layer 130A/130B; a second through-via 136 (second one from the right sidewall of 124) extending through the insulating layer 142 and the semiconductor layer 124 and electrically connected to the power delivery network layer 130A/130B (see Fig. 12 and paragraph 0041); a logic element 126 (for example a transistor as discussed in paragraph 0037) on the semiconductor layer 124 and electrically connected to the first through-via 136 (second one from the right sidewall of 124) ; and a passive element, trench capacitors 128, on the semiconductor layer 124 and electrically connected to the second through-via 136 (second one from the right sidewall of 124) (see paragraphs 0037 and 0038). Chen et al. fails to disclose the newly added limitation with respect to the laterally spaced apart. However, Yeh et al. discloses a PDN network where in Figs. 2 and 3 and in paragraphs 0012,0013,0022, 0023,0025 and 0026 the required laterally spaced apart limitation is disclosed,
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the laterally spaced apart limitation in Chen et al., as taught by Yeh et al. in order to bring BSPDN network to active and passive elements reliably.
Regarding Claim 2, in paragraph 0012 of Chen et al., a signal wiring layer i.e. RDL 110 or RDL 106, electrically connected to the logic element 126 (i.e. transistors see paragraph 0037) and the passive element (i.e. trench capacitors 128, see paragraph 0037), wherein the signal wiring layer 106 is on a side of the logic element 126 and the passive element 128 opposite the first through-via and the second through-via.
Regarding Claim 3, in Chen et al., the semiconductor layer 124 includes silicon (see paragraph 0037), and the insulating layer 142 includes silicon oxide (see paragraph 0042)
Regarding Claim 4, in Chen et al, the logic element 126 (i.e. transistor) includes: a semiconductor substrate (see paragraph 0037); an active pattern disposed on the semiconductor substrate (see paragraph 0037); a power rail, i.e. 130A connected to the first through-via 136 and having a portion in the semiconductor substrate; and a contact electrically connecting the power rail and the active pattern to each other (see paragraph 0037, lines 10-23).
Regarding Claim 5, in Chen et al., a lower surface of the insulating layer 142 and a lower surface of the semiconductor layer 124 are coplanar with each other (please note that with respect to lower surface, this has not been tied to any specific orientation and hence examiner can take “flipped” and/or regular orientations of elements 142 and 124 to arrive at the coplanar limitations)
Regarding Claim 6, in Chen et al., the first through-via includes 136 (specifically the third one from the right sidewall of element 124) a material different from a material of the second through-via 136 (specifically the second through via from the right sidewall of element 124)(also see paragraph 0038)
Regarding Claim 7, in Chen et al, a maximum width of the first through-via 136 (specifically the third one from the right sidewall of element 124) is different from a maximum width of the second through-via (specifically the second through via from the right sidewall of element 124 (see also paragraph 0053. Please also note that “width” limitation is not tied to a specific orientation)
Regarding Claim 8, in Chen et al, the maximum width of the first through-via is smaller than the maximum width of the second through-via. (again, the “width” limitation is not tied to any geometrical portion of “through-via” and hence examiner can take any geometrical relationship to arrive at this limitation. Please also see paragraph 0053).
Regarding Claim 9, in Fig 12, (and Fig 8) (and paragraph 0041) Chen et al. discloses a semiconductor device comprising: a substrate layer 124 including an insulating layer 142 (see Fig. 8) and a semiconductor layer 124, wherein the substrate layer includes: a first area (left half portion of the Figure 12) including the semiconductor layer 124; and a second area (right half of the Figure 12) different from the first area and including a stack of the insulating layer142 and the semiconductor layer 124; a logic element 126 (transistor, see paragraphs 0037 and 0053) and a passive element 128 (trench capacitors, see paragraphs 0037 and 0053) on a first (upper/top) surface of the substrate layer 124, wherein the logic element 126 is disposed on the first area (left half portion) of the substrate layer 124 and the passive element 128 is disposed on the second area (the right half portion) of the substrate layer 124; a signal wiring layer 130B on the first (top or upper) surface of the substrate layer 124 and electrically connected to the logic element and the passive element (see paragraphs 0037 and 0041); and a power delivery network layer 130A on a second (lower or bottom) surface of the substrate layer 124 opposite to the first surface. Chen et al. fails to disclose the newly added limitation with respect to the lateral. However, Yeh et al. discloses a PDN network where in Figs. 2 and 3 and in paragraphs 0012,0013,0022, 0023,0025 and 0026 the required lateral limitation is disclosed,
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the lateral limitation in Chen et al., as taught by Yeh et al. in order to bring BSPDN network to active and passive elements reliably.
Regarding Claim 10, in Chen et al, a first through-via 136 (specifically the third one from the right sidewall of element 124) extending through the semiconductor layer of the first area and electrically connected to the power delivery network layer and the logic element 126 (see paragraphs 0037, 0041); and a second through-via 136 (the second on from the right sidewall of element 124) extending through the stack of the second area (right half portion of 124) and electrically connected to the power delivery network 130B layer and the passive element 128 (see paragraph 0037 and 0041)
Regarding Claim 11, in Chen et al, the logic element 126 includes: a semiconductor substrate; an active pattern on the semiconductor substrate; a power rail connected to the first through-via and having a portion in the semiconductor substrate (paragraph 0037); and a contact electrically connecting the power rail and the active pattern to each other (see paragraph 0037, lines 10-23).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 5/28/2026
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