DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group II directing to claims 7-14 in the reply filed on February 06, 2026 is acknowledged. The traversal is on the ground(s) that “applicants note that Claims 1 and 7 recite many common features, and that no serious search burden would result”. This is not found persuasive because the inventions require a different field of search (e.g., searching different CPC groups/subgroups or electronic resources, or employing different search strategies or search queries). They require different keyword searches. Furthermore, a search for an electronic chip and/or an electrical interconnection layer and/or first/second metal layer on a substrate is not likely to find art pertinent to a method of making a SiP-type electronic device by using a carrier substrate and later detaching the carrier substrate in order to fabricate the final packaged device.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-6 directed to the non-elected group, are thereby withdrawn. Currently claims 1-14 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/13/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, Chen-Hua (US 20220199461 A1) “Yu et al.” in view of Mallik, Debendra (US 20210035881 A1) “Mallik et al.” further in view of Lin, Yaojian (US 20150021754 A1) “Lin et al.”.
Regarding Independent Claim 7, Yu et al. Figs. 5-8 discloses a method for making a SiP-type electronic device (“a semiconductor package” ¶ [0079]), comprising at least:
affixing an electronic chip (“one or more integrated passive devices (IPDs) 80 (see FIG. 5)” ¶ [0026]) over a first substrate (“a first carrier substrate 102” ¶ [0027]) such that an electrical interconnection face of the electronic chip 80 is arranged on the side of the first substrate 102;
encapsulating the electronic chip in an encapsulation material (“encapsulant 118 encapsulates…the IPDs 80” ¶ [0033]);
However, Yu et al. does not disclose, making at least one first metal layer over the encapsulation material and the electronic chip;
making at least one second metal layer over a second substrate;
directly bonding the first and second metal layers against one another;
detaching the first substrate off the electronic chip and the encapsulation material;
making at least one redistribution layer electrically coupled to the electrical interconnection face of the electronic chip;
making electrical interconnection elements over the redistribution layer such that the electrical interconnection elements are electrically coupled to the electronic chip by the redistribution layer.
In the similar field of endeavor of packaged semiconductor devices, Mallik et al. Figs. 2A-2F discloses, making at least one first metal layer over the encapsulation material and the electronic chip 223 (“a back-side bond material 260 is in contact with each chip substrate 223, and is also in contact with mold material 250 within spaces between IC chips 221, 222” ¶ [0027]);
making at least one second metal layer 275 (“Bond material 275 may have any of the above compositions (e.g., solder, Cu, Au, SiO.sub.2, polymer) etc.” ¶ [0031]) over a second substrate (“a bulk substrate 270” ¶ [0031]);
directly bonding the first and second metal layers (“a bond material 275 is bonded to back-side bond material 260” ¶ [0031]) against one another;
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the interconnect structures of Yu et al. including the first and second metal layer bonded together of Mallik et al. in order to improve thermal conduction and/or dissipation of heat from the IC chips, the integrated heat spreader offers both mechanical and thermal advantages (Mallik et al. ¶ [0033]).
However, Mallik et al. does not disclose, detaching the first substrate off the electronic chip and the encapsulation material;
making at least one redistribution layer electrically coupled to the electrical interconnection face of the electronic chip;
making electrical interconnection elements over the redistribution layer such that the electrical interconnection elements are electrically coupled to the electronic chip by the redistribution layer.
In the similar field of endeavor of packaged semiconductor devices, Lin et al. Figs. 12a-12f discloses detaching the first substrate off the electronic chip and the encapsulation material (“In FIG. 12c, carrier 250 and interface layer 252 are removed” ¶ [0085]);
making at least one redistribution layer electrically coupled to the electrical interconnection face of the electronic chip (“An electrically conductive layer or RDL 264” ¶ [0087]);
making electrical interconnection elements (“a build-up interconnect structure 260 is formed over semiconductor die 224 and encapsulant 256” ¶ [0086]) over the redistribution layer 264 such that the electrical interconnection elements are electrically coupled to the electronic chip by the redistribution layer (Fig. 12d shows 224 and 268 are coupled by 264).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the interconnect structures of Yu et al. as modified by Mallik et al. in order to provide a low resistive interconnect to conductive layer, as well as a barrier to solder diffusion and seed layer for solder wettability (Lin et al. ¶ [0089]).
Regarding Claim 8, Yu et al. as modified by Mallik et al. and Lin et al. discloses the limitations of claim 7. However, Yu et al. does not disclose,
making the first metal layer includes at least depositing a first copper layer over the encapsulation material and the electronic chip, and
making the second metal layer includes at least depositing a second copper layer over the second substrate.
In the similar field of endeavor of packaged semiconductor devices, Mallik et al. Figs. 2A-2F discloses, making the first metal layer includes at least depositing a first copper layer (“bond material 260 comprises a layer of metallization (e.g., Cu, Au, In, Sn, Ag, Bi, or Ni, and alloys thereof)” ¶ [0027]) over the encapsulation material 250 and the electronic chip 223 (“a back-side bond material 260 is in contact with each chip substrate 223, and is also in contact with mold material 250 within spaces between IC chips 221, 222” ¶ [0027]);
making the second metal layer 275 includes at least depositing a second copper layer (“Bond material 275 may have any of the above compositions (e.g., solder, Cu, Au, SiO.sub.2, polymer) etc.” ¶ [0031]) over the second substrate (“a bulk substrate 270” ¶ [0031]);
directly bonding the first and second metal layers (“a bond material 275 is bonded to back-side bond material 260” ¶ [0031]) against one another;
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the interconnect structures of Yu et al. including the first and second metal layer bonded together of Mallik et al. in order to improve thermal conduction and/or dissipation of heat from the IC chips, the integrated heat spreader offers both mechanical and thermal advantages (Mallik et al. ¶ [0033]).
Regarding Claim 9. Yu et al. as modified by Mallik et al. and Lin et al. discloses the limitations of claim 8. However, Yu et al. does not disclose, wherein directly bonding the first and second metal layers against one another corresponds to directly bonding the first and second copper layers against one another.
In the similar field of endeavor of packaged semiconductor devices, Mallik et al. Figs. 2A-2F discloses, wherein directly bonding the first and second metal layers against one another corresponds to directly bonding the first and second copper layers against one another (“Cu—Cu bonding” ¶ [0030]; “a bond material 275 is bonded to back-side bond material 260” ¶ [0031]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the interconnect structures of Yu et al. including the first and second metal layer bonded together of Mallik et al. in order to improve thermal conduction and/or dissipation of heat from the IC chips, the integrated heat spreader offers both mechanical and thermal advantages (Mallik et al. ¶ [0033]).
Regarding Claim 11. Yu et al. as modified by Mallik et al. and Lin et al. discloses the limitations of claim 7. However, Yu et al. does not disclose, wherein the encapsulation of the electronic chip includes at least depositing the encapsulation material over the electronic chip, then flattening the encapsulation material.
In the similar field of endeavor of packaged semiconductor devices, Mallik et al. Figs. 2A-2F discloses, wherein the encapsulation of the electronic chip includes at least depositing the encapsulation material over the electronic chip, then flattening the encapsulation material (“an overmold planarization process has thinned mold material 250” ¶ [0027]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the interconnect structures of Yu et al. including the planarization process to obtain thinned mold material of Mallik et al. in order to expose a back side of each of IC chips (Mallik et al. ¶ [0027]).
Regarding Claim 12. Yu et al. as modified by Mallik et al. and Lin et al. discloses the limitations of claim 7. Yu et al. further discloses, wherein several electronic chips are simultaneously affixed on the first substrate such that an electrical interconnection face of each of the electronic chips is arranged on the side of the first substrate (“The interconnect structure 100 includes one or more interconnect components 50 (see FIG. 1) and/or one or more integrated passive devices (IPDs) 80 (see FIG. 5). In FIGS. 2 through 8, a first region 101A and a second region 101B are illustrated, and an interconnect structure 100 may be formed in each of the regions 101A and 101B.” ¶ [0026]), and wherein the other steps of the method are collectively implemented for all electronic chips, and further including, after making the electrical interconnection elements (claim 7 discloses the other steps of the method are collectively implemented for all electronic chips, and further including, after making the electrical interconnection elements), a step of cutting the obtained structure so as to obtain several distinct SiP-type electronic devices each including one or more electronic chip(s) (“A singulation process may be performed to singulate individual interconnect structures 100 such as that shown in FIG. 9.” ¶ [0026]).
Regarding Claim 13. Yu et al. as modified by Mallik et al. and Lin et al. discloses the limitations of claim 11. However, Yu et al. does not disclose, wherein, when the electronic chips have different thicknesses, flattening the encapsulation material is stopped at the electronic chip(s) having the largest thickness.
In the similar field of endeavor of packaged semiconductor devices, Lin et al. Figs. 12a-12f discloses wherein, when the electronic chips 224 have different thicknesses, flattening the encapsulation material is stopped at the electronic chip(s) having the largest thickness (Figs. 12f shows encapsulant or molding compound 256 is flatten and stops at the thickest 224).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the interconnect structures of Yu et al. as modified by Mallik et al. in order to remove damage to base material of semiconductor die. Back surface of semiconductor die, having a reduced height with respect to adjacent semiconductor die, remains covered by encapsulant (Lin et al. ¶ [0092]).
Regarding Claim 14. Yu et al. as modified by Mallik et al. and Lin et al. discloses the limitations of claim 7. Yu et al. does not disclose, further including, after making the electrical interconnection elements, etching the second substrate forming structures promoting heat exchanges with the external environment, and/or wherein the second substrate includes at least one integrated vapor chamber.
In the similar field of endeavor of packaged semiconductor devices, Mallik et al. Fig. 4 discloses, further including, after making the electrical interconnection elements (“LTS may be similarly enlisted for subsequently formed SMT solder interconnects of a package substrate” ¶ [0029]), etching the second substrate forming structures (124) promoting heat exchanges with the external environment, and/or wherein the second substrate (116) includes at least one integrated vapor chamber (“etched into bulk substrate 270 with any suitable technique. As shown, channels 410 place a coolant inlet 405 located over IC chip 221 in fluid communication with a coolant outlet 410 located over IC chip 222. Coolant inlet 405 and outlet 410 each open into the opposing side of heat spreader 280. The Multi-chip unit 401 may therefore be fu” ¶ [0036]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the interconnect structures of Yu et al. as modified by Mallik et al. and Lin et al. including the planarization process to obtain thinned mold material of Mallik et al. in order to facilitate heat extraction from the multi-chip unit (Mallik et al. ¶ [0036]).
Claims 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Chen-Hua (US 20220199461 A1) “Yu et al.” in view of Mallik, Debendra (US 20210035881 A1) “Mallik et al.” further in view of Lin, Yaojian (US 20150021754 A1) “Lin et al.” further in view of Kim, Jin Young (US 20160211221 A1) “Kim et al.” and Enquist; Paul M. (US 20170179029 A1) “Enquist et al.”.
Regarding Claim 10. Yu et al. as modified by Mallik et al. and Lin et al. discloses the limitations of claim 8. However, Yu et al. does not disclose, wherein:
making the first metal layer further includes depositing a first gold layer over the first copper layer, and
making the second metal layer further includes depositing a second gold layer over the second copper layer, and- directly bonding the first and second metal layers against one another corresponds to directly bonding the first and second gold layers against one another.
In the similar field of endeavor of packaged semiconductor devices Kim et al. Figs. 10E-10F discloses an upper seed layer 30 may be formed on the top surface of the insulation layer 730. The upper seed layer 30 may, for example, comprise any or all characteristics of the first seed layer 20 and/or the second seed layer 21 discussed herein. For example, the upper seed layer 30 may comprise copper (e.g., a plated copper layer or foil). Also for example, the upper seed layer 30 may comprise one or more layers of any of a variety of metals (e.g., copper, silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, alloys thereof, etc..
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the process of making the first metal layer further includes depositing a first gold layer over the first copper layer, and the process of making the second metal layer further includes depositing a second gold layer over the second copper layer, and- directly bonding the first and second metal layers against one another corresponds to directly bonding the first and second gold layers against one another of Yu et al. as modified by Mallik et al. and Lin et al. with the seed layer of Kim et al. in order to offer numerous advantages and distinctions from prior low temperature wafer bonding techniques. The metal-to-metal direct bonding is spontaneous and requires no external forces at room temperature. The pressure applied on the metal posts that is required for metal-to-metal bonding is generated by bonding process itself, and not external forces. The metal-to-metal direct bonding described above can be performed under ambient conditions and the following are realized: wafer level or die size bonds, strong metallic Au—Au, Cu—Cu or metal-to-metal bonds formed at room temperature (Enquist et al. ¶ [00118]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YARA J. GREEN can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893