DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-11 of copending Application No. 18/463,138 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because
Regarding Claim 1, both the instant claim 1 and claims 1, 4, 5 and 6 of ‘138 recite semiconductor device, comprising: a first electrode; a second electrode separated from the first electrode; a first region located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region, a plurality of third semiconductor regions located on the portion of the second semiconductor region, the plurality of third semiconductor regions being of the first conductivity type, a gate electrode facing one of the plurality of third semiconductor regions via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, a conductive part facing an other one of the plurality of third semiconductor regions via an insulating layer in the second direction, the conductive part being electrically connected with the second electrode, a fourth semiconductor region located on the one of the plurality of third semiconductor regions, the fourth semiconductor region being of the second conductivity type, a fifth semiconductor region located on the one of the plurality of third semiconductor regions, the fifth semiconductor region being of the first conductivity type, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the one of the plurality of third semiconductor regions, and a sixth semiconductor region located on the other one of the plurality of third semiconductor regions, the sixth semiconductor region being of the second conductivity type, a length of the sixth semiconductor region in a third direction being greater than a length of the fourth semiconductor region in the third direction, the third direction being perpendicular to the first and second directions; and a second region located on another portion of the first electrode and positioned between the first electrode and the second electrode, the second region including a seventh semiconductor region of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region, another portion of the second semiconductor region located on the seventh semiconductor region, and an eighth semiconductor region located on the other portion of the second semiconductor region, the eighth semiconductor region being of the first conductivity type.
Regarding Claim 2, both the instant claim 2, and claims 1 and 3 of ‘138 recite, the fourth semiconductor region and the fifth semiconductor region are alternately arranged in the third direction.
Regarding Claim 3, both the instant claim 3 and claims 1-5 of ‘138 recite, the fifth semiconductor regions are provided respectively on the plurality of third semiconductor regions, and a length in the second direction of the fifth semiconductor region positioned on the other one of the plurality of third semiconductor regions is less than a length in the second direction of another of the fifth semiconductor regions positioned on the one of the plurality of third semiconductor regions.
Regarding Claim 4, both the instant claim 4 and claims 1-5 of ‘138 recite, a plurality of the fifth semiconductor regions is arranged in the third direction on the other one of the plurality of third semiconductor regions, and the sixth semiconductor region is located around the plurality of fifth semiconductor regions along a first plane perpendicular to the first direction.
Regarding Claim 5, both the instant claim 5 and claims 1-5 and 7 of ‘138 recite, wherein the first region includes: a first part in which the gate electrode, the fifth semiconductor region, the fourth semiconductor region, and the one of the plurality of third semiconductor regions are located; and a second part in which the conductive part, the sixth semiconductor region, and the other one of the plurality of third semiconductor regions are located, and the second part is positioned between the first part and the second region.
Regarding Claim 6, both the instant claim 6 and claims 1-6 of ‘138 recite, a length in the second direction of the second part is greater than a distance in the first direction between the first electrode and the second electrode.
Regarding Claim 7, both the instant claim 7 and claims 8 and 11 of ‘138 recite a semiconductor device, comprising: a first electrode; a second electrode separated from the first electrode; a first region located on a portion of the first electrode and positioned between the first electrode and the second electrode, the first region including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a portion of the second semiconductor region being located on the first semiconductor region, a plurality of third semiconductor regions located on the portion of the second semiconductor region, the plurality of third semiconductor regions being of the first conductivity type, a gate electrode facing one of the plurality of third semiconductor regions via a gate insulating layer in a second direction perpendicular to a first direction, the first direction being from the first electrode toward the second electrode, a conductive part facing another one of the plurality of third semiconductor regions via an insulating layer in the second direction, the conductive part being electrically connected with the second electrode, a fourth semiconductor region located on the one of the plurality of third semiconductor regions, the fourth semiconductor region being of the second conductivity type, a fifth semiconductor region located on the one of the plurality of third semiconductor regions, the fifth semiconductor region being of the first conductivity type, a first-conductivity-type impurity concentration of the fifth semiconductor region being greater than a first-conductivity-type impurity concentration of the one of the plurality of third semiconductor regions, and a sixth semiconductor region located on the other one of the plurality of third semiconductor regions, the sixth semiconductor region being of the first conductivity type, a first-conductivity-type impurity concentration of the sixth semiconductor region being greater than a first-conductivity-type impurity concentration of the other one of the plurality of third semiconductor regions, an area of the sixth semiconductor region per unit area being greater than an area of the fifth semiconductor region per unit area at a first plane perpendicular to the first direction; and a second region located on another portion of the first electrode and positioned between the first electrode and the second electrode, the second region including a seventh semiconductor region of the second conductivity type, the seventh semiconductor region having a higher second-conductivity-type impurity concentration than the second semiconductor region, another portion of the second semiconductor region located on the seventh semiconductor region, and an eighth semiconductor region located on the other portion of the second semiconductor region, the eighth semiconductor region being of the first conductivity type.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 1/7/2026