DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 06/15/2026.
Claims 1-20 are pending in this application.
Applicant made a provisional election to prosecute the
invention of Group I, claims 1-15, is acknowledged.
Because Applicant did not distinctly and specifically point out the supposed error in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claims 16-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 10/13/2023. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Foreign Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The specification is objected to for the following reason:
The drawings show Fig. 37A, Fig. 37B, and the brief description of the drawings at paragraph [0007] combinedly recites Figs. 8-44.
MPEP 608.01(f) requires a brief description of Fig. 37A, Fig. 37B be provided. Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by IM et al. (US 2019/0115325)
Regarding claim 1, IM discloses a semiconductor package, comprising:
a lower substrate 101 (see fig. 17) including a lower interconnection layer (to which connecting elements 310, 113, 103 are connected; see paras. 0087-0091);
an upper substrate 301 on the lower substrate 101, including a first surface 300U and a second surface 300L opposite to each other;
a recessed surface R1/R1_U having a step difference R1_S from the second surface 300L;
a through-hole 301h extending from the recessed surface R1_U to the first surface 300U and an upper interconnection layer 311, 313, 321, 323 electrically connected to the lower interconnection layer (via connecting elements 310);
a semiconductor chip 110 disposed between the recessed surface of the upper substrate 301 and the lower substrate 101, and including connection pads 113 electrically connected to the lower interconnection layer;
an interconnect structure 310 disposed between the second surface 300L of the upper substrate 301 and the lower substrate 101, and electrically connecting the lower interconnection layer to the upper interconnection layer; and
an insulating member 121 & 123 & 127 including a first portion 121 and/or 123 covering at least a portion of each of the semiconductor chip 110 and the interconnect structure 310 between the upper substrate and the lower substrate, a second portion 127 extending from the first portion into the through-hole 301h, and a third portion 127 (on top of the second substrate 301) extending from the second portion and covering at least a portion of the first surface 300U of the upper substrate 301.
Regarding claim 2, IM discloses the semiconductor package of claim 1, wherein bump structures 113 electrically connected to the connection pads of the semiconductor chip, wherein the first portion 121 configured to encapsulate at least a portion of the bump structures 113. See fig. 17.
Regarding claim 3, IM discloses the semiconductor package of claim 2, wherein the bump structures 113 are spaced apart from each other with an equal distance therebetween. See fig. 17.
Regarding claim 4, IM discloses the semiconductor package of claim 1, wherein a width of a lower end of the third portion in contact with the first surface 300U of the upper substrate 301 is greater than a diameter of the through-hole 301h. See fig. 17.
Regarding claim 5, IM discloses the semiconductor package of claim 1, wherein the through-hole 301h extends perpendicular to the recessed surface R1_U. See fig. 17.
Regarding claim 6, IM discloses the semiconductor package of claim 1, wherein a width of the recessed surface R1_U is greater than a width of the semiconductor chip 110. See fig. 17.
Regarding claim 7, IM discloses the semiconductor package of claim 1, further comprising:
an upper package 220 disposed on the upper substrate 301; and
upper connection bumps 205_3 electrically connecting the upper package 220 to the upper interconnection layer 311/313, wherein a height of the third portion (which might be chosen as a non-highest height of the third portion) is lower than a height (the highest height) of the upper connection bumps. See fig. 17.
Regarding claim 8, IM discloses a semiconductor package, comprising:
a lower substrate 101 (see fig. 17) including a lower interconnection layer (to which connecting elements 310, 113, 103 are connected; see paras. 0087-0091);
a semiconductor chip 110 disposed on the lower substrate 101 and electrically connected to the lower interconnection layer;
an upper substrate 301 disposed on the semiconductor chip 110 and including interconnection pads 331 surrounding a region R1_U overlapping the semiconductor chip 110, and at least one through-hole 301h spaced apart from the interconnection pads 331;
at least one mold line 127 (portion above the second substrate 301) disposed on the upper substrate 301 and spaced apart from the interconnection pads 331 and extending in a first direction (laterally) from the through-hole 301h;
an encapsulant 121 & 123 & 127 configured to encapsulate at least a portion of the semiconductor chip 110 between the upper substrate 301 and the lower substrate 101 and connected to the mold line 127 through the through-hole 301h.
Regarding claim 9, IM discloses the semiconductor package of claim 8, wherein the at least one through-hole includes a plurality of through-holes (comprising through hole 301h and via holes forming vias 323) spaced apart from each other in the first direction. See fig. 17.
Regarding claim 10, IM discloses the semiconductor package of claim 9, wherein the plurality of through-holes are aligned in a row in the first direction. See fig. 17.
Regarding claim 11, IM discloses the semiconductor package of claim 10, wherein at least some of through-holes among the plurality of through-holes partially overlap in the first direction. See fig. 17.
Regarding claim 12, IM discloses the semiconductor package of claim 8, wherein the at least one through-hole includes a plurality of through-holes (comprising through hole 301h and via holes forming vias 323) spaced apart from each other in a second direction intersecting the first direction. See fig. 17.
Regarding claim 15, IM discloses the semiconductor package of claim 8, wherein the at least one mold line 127 extends to at least one side end of the upper substrate in a first direction. See fig. 17.
Allowable Subject Matter
7. Claims 13-14 are allowable.
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed semiconductor package (in addition to the other limitations in the claim):
wherein the at least one mold line includes a plurality of mold lines spaced apart from each other and extending in the first direction from the plurality of through-holes.
Conclusion
8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 July 10, 2026
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