DETAILED ACTION
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/20/2026 and 08/20/2026 have been entered.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
2. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. U.S. Patent Application Publication 2023/0268424 A1 (the ‘424 reference, of record).
The reference discloses in Fig. 11 and related text an integrated circuit (IC) structure as claimed.
Referring to claim 1, the ‘424 reference discloses an integrated circuit (IC) structure, comprising:
a fin structure (comprising fins 20’s, Fig. 11, para [10] (paragraph(s) [0010])) disposed over a substrate (12, para [9]), wherein the fin structure (20’s) includes first and second segments (left segment and right segment of fins 20’s of a high voltage (HV) transistor (~14) in HV transistor region 14 (para [9])) and a bottom surface between the first and second segments, and the bottom surface includes a plurality of recesses (32, 38, para [14, 16]);
a dielectric material (30, 36, para [14, 16]) disposed between the first and second segments (said left segment and said right segment of fins 20’s) of the fin structure (20’s), wherein the dielectric material is disposed on the bottom surface and in the plurality of recesses; and
a gate structure (58/46, para [20, 24]) disposed over the first segment of the fin structure, wherein the gate structure (58/46) covers a top surface and side surfaces of the first segment of the fin structure (20’s), and the gate structure (58/46), the first segment of the fin structure, and the second segment of the fin structure form a field-effect transistor (~14).
Referring to claim 2, the reference further discloses a source (60, para [24-26]) disposed in the first segment (said left segment of fins 20’s) of the fin structure and a drain (60) disposed in the second segment (said right segment of fins 20’s) of the fin structure (20’s).
Referring to claim 3, the reference further discloses that the bottom surface and the dielectric material (30, 36, closest to the gate 58 in the HV transistor region 14) are disposed between the source (60) and the drain (60).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
3. Claim 4 is rejected under 35 U.S.C. §103 as being unpatentable over Hsu et al. U.S. Patent Application Publication 2023/0268424 A1 (the ‘424 reference) in view of Tsuda U.S. Patent Application Publication 20180342526, both of record.
Referring to claim 4, the ‘424 reference discloses the fin structure (20’s) as detailed above for claim 1, but does not disclose that the fin structure has a height ranging from about 100 nm to about 120 nm.
Tsuda, in disclosing an integrated circuit comprising a fin structure F (Fig. 17), discloses that the fin structure has a height ranging from about 100 nm to about 250 nm (para [102]), thereby teaching that about 100 nm to about 250 nm is a range of height suitable for the fins.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s fin structure 20 having a height ranging from about 100 nm to about 250 nm. One would have been motivated to make such a modification in view of the teachings in Tsuda that about 100 nm to about 250 nm – overlapping and meeting the claim range of about 100 nm to about 120 nm - is a range of height suitable for the fins.
Allowable Subject Matter
4. Claims 8-19 are allowable over the prior art of record.
Claims 5-7 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an integrated circuit (IC) structure with all exclusive limitations as recited in claims 5, 6, and 21;
which may be characterized (claims 5 and 21) in that the plurality of recesses define a plurality of fins, and each fin has a height ranging from about 5 nm to about 20 nm, and (claim 6) in that the gate structure comprises first, second, third, and fourth segments, the first and second segments of the gate structure are disposed over the first segment of the fin structure, and the third and fourth segments of the gate structure are disposed over the second segment of the fin structure.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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09-03-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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