DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Applicant’s amendment filed September 9, 2026.
Claim Objections
The objection to claim 7 has been withdrawn due to the amendment filed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 8-11 and 18-19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cheng (US 2019/0312123 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In regard to claim 1, Cheng teaches a semiconductor device 5 comprising: a gate cut portion 62/64 disposed between a first gate region 22 and a second gate region 22; wherein the gate cut portion 62/64 comprises a dielectric liner layer 62 disposed around a vacant area 64; wherein the dielectric liner layer 62 singularly encloses the vacant area 64; and wherein the gate cut portion 62/64 isolates the first gate region 22 from the second gate region 22 (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 2, Cheng teaches the vacant area 64 comprising air (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 3, Cheng teaches the first gate region 22 and the second gate region 22 contacting the dielectric liner layer 64 of the gate cut portion 62/64 (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 8, Cheng teaches part of the gate cut portion 62/64 disposed in an isolation region 36 (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 9, Cheng teaches a spacer layer 28 disposed between the isolation region 36 and the part of the gate cut portion 62/64 (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 10, Cheng teaches the part of the gate cut portion 62/64 disposed in the isolation region 36 comprises a pinched-off portion of the dielectric liner layer 62 (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 11, Cheng teaches a cap layer 66 disposed on the first gate region 22, the second gate region 22 and the gate cut portion 62-64, wherein the cap layer 66 contacts the gate cut portion 62/64 (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 18, Cheng teaches a semiconductor device 5 comprising: a first transistor comprising a first gate region 22; a second transistor comprising a second gate region 22; and an isolation structure disposed between and contacting the first gate region 22 and the second gate region 22, wherein the isolation structure comprises a dielectric liner layer 62 disposed around a vacant area 64, and wherein the dielectric liner layer 62 singularly encloses the vacant area 64 (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
In regard to claim 19, Cheng teaches the vacant area 64 comprising air (Figure 23, pages 3-7, paragraphs [0042]-[0109]).
Allowable Subject Matter
Claims 6-7, 12-14, 16-17 and 21 are allowed.
The following is an examiner’s statement of reasons for allowance:
In regard to claim 6, the prior art of record (Cheng (US 2019/0312123 A1)) does not disclose, make obvious, or otherwise suggest the structure of the applicant's claimed invention together with the other limitations of the dependent claims 2-5 and 8-11, such as the configuration of the gate cut portion, gate regions, dielectric liner layer, vacant area, source/drain contact, source/drain regions and semiconductor placeholder layer;
In regard to claim 7, the prior art of record (Cheng (US 2019/0312123 A1)) does not disclose, make obvious, or otherwise suggest the structure of the applicant's claimed invention, such as the configuration of the gate cut portion, gate regions, dielectric liner layer, vacant area, source/drain regions, backside power delivery network layers and backside source/drain contact;
In regard to claim 12, the prior art of record (Ando et al. (US 2019/0157414 A1)) does not disclose, make obvious, or otherwise suggest the structure of the applicant's claimed invention together with the other limitations of the dependent claims 13-14, 16-17 and 21, such as the configuration of the nanosheet structures, channel layers, gate cut portion, gate regions, gate structures, dielectric liner layer, source/drain regions and vacant area; and
Claims 4 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5 is objected to as being dependent upon objected claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The following patents are cited to further show the state of the art with respect to semiconductor devices:
Frougier et al. (US 2020/0152504 A1) Lin et al. (US 2023/0101278 A1)
Xie et al. (US 10,373,875 B1) You et al. (US 2022/0367457 A1).
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IMS
October 7, 2026
/IDA M SOWARD/Primary Examiner, Art Unit 2898
