DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 are pending in this application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 18 is objected to because of the following informalities:
Re claim 18 cite a limitation in line 13” the conductive material “ should read “conductive material layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, 11-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Derakhshandeh (US 20210159207 A1) in view of Yoo et al (US 20190043831 A1).
Re claim 1 Derakhshandeh teaches, a semiconductor package (fig 5) [comprising: a first semiconductor chip (1, fig 5) [0046], wherein the first semiconductor chip (1, fig 5) [0031] extends in each of first (z-axis) and second directions (x-axis) that intersect each other;
a second semiconductor chip (20, fig 5) [0046] stacked on the first semiconductor chip (1, fig 5) [0046] in a third direction (y-direction) perpendicular to each of the first (x-axis) and second directions (z-axis), wherein the second semiconductor chip (20, fig 5) includes a first area (middle area, fig 5) and a second area (corner area) that is adjacent to and extends around the first area (middle area, fig 5);
a bump structure (10/6, 11/12, fig 3 and 5) [0046] between the first (1, fig 5) and second semiconductor chips (20, fig 5); and
wherein the bump structure (10/6, 1/12 13, fig 5) includes a first bump structure (10/6, fig 5) overlapping the first area (middle area, fig 5) in the third direction (y-direction), and a second bump structure (11/12, fig 5) overlapping the second area (corner area) in the third direction (y-axis),
wherein the first bump structure (10/6, fig 5) and the second bump structure (11/12, fig 5) are spaced apart from each other (fig 5), and
wherein a thickness of the second bump structure (thickness of 11 fig 5) in the third direction (y-direction) is larger (see fig 5) than a thickness (thickness of 10, fig 5) of the first bump structure (10/6, fig 3 and 5) in the third direction (y-axis).
Derakhshandesh does not teach a conductive material layer between the first and second semiconductor chips, wherein the conductive material layer is on the bump structure.
Yoo teaches a conductive material layer (170, fig 1) [0031] between the first and second semiconductor chips (between 131 and 133, fig 1) [0031], wherein the conductive material layer is on the bump structure (141/116, fig 1) [0016, 0026].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yoo into the structure of Derakhshandesh to include a conductive material layer between the first and second semiconductor chips, wherein the conductive material layer is on the bump structure as claimed.
The ordinary artisan would have been motivated to modify Derakhshandesh based in teaching Yoo in the above manner for the purpose of improving the reliability of the device [0034]
Re claim 2 Derakhshandesh in view of Yoo teaches, the semiconductor package of claim 1, wherein a maximum width of the second bump structure (11/12, fig 5) [Derakhshandesh, 0046] in the first direction (x-axis) is greater than a maximum width of the first bump structure (10/6 , fig 5) [Derakhshandesh 0046] in the first direction (x-axis).
Re claim 3. Derakhshandesh in view of Yoo teaches, the semiconductor package of claim 1, wherein the first bump structure (10/6, fig 5) [0036] includes a first solder bump (10, fig 5) [0036] between a first-first wiring pad (top 6, fig 5) [0036] of the first semiconductor chip (1, fig 5) and a first-second wiring pad (bottom 6 fig 5) of the second semiconductor chip (20, fig 5) and
wherein the second bump structure (11/12, fig 5) includes a second solder bump (11, fig 5) [0034]between a second-first wiring pad (top 12,fig 5) of the first semiconductor chip (1, fig 5) and a second-second wiring pad (bottom 12, fig 5) of the second semiconductor chip (20, fig 5) [Derakhshandesh ,0034].
Re claim 4. Derakhshandesh in view of Yoo teach the semiconductor package of claim 3,
wherein the second-first wiring pad (top 12, fig5)[ Derakhshandesh, 0034] of the first semiconductor chip (1, fig 5) includes a plurality of second-first wiring sub-pads (left and right top 12, fig 5) that are spaced apart from each other (see fig 5),
wherein the second solder bump (11, fig 5) is between the plurality of second-first wiring sub- pads (left and right top 12, and wherein a thickness of the second solder bump (11, fig 3) in the third direction (y-direction) is larger than a thickness of the first solder bump (10, fig 3) [Derakhshandesh] in the third direction.
Re claim 6 Derakhshandesh in view of Yoo teach the semiconductor package of claim 4, each of the plurality of second-first wiring sub-pads (left and right top 12, fig 5) [0034] has a rectangular shape (see fig 5) in a plan view of the semiconductor package (fig 5) [Derakhshandesh, 0034].
Re claim 7 Derakhshandesh in view of Yoo teach the semiconductor package of claim 1,
wherein the first bump structure (10/6, fig 5)[ Derakhshandesh , 0032] is electrically connected to the first and second semiconductor chips (fig 5) [Derakhshandesh, 0033], and
wherein the second bump structure (12, fig 5) [0033] is electrically insulated (dummy contact) [Derakhshandesh , 0033] from the first and second semiconductor chips (fig 5) [Derakhshandesh, 0033].
Re claim 8 Derakhshandesh in view of Yoo teach the semiconductor package of claim 1, wherein the conductive material layer (170 , fig 1) [Yoo, 0031] includes a resin layer (polymer resin, thermosetting resin, a thermo-plastic resin,) [Yoo, 0031] and a filler (conductive particles comprise Ni, Au, Ag, or Cu in the resin layer (fig 1) [Yoo 0031].
Re claim 9 Derakhshandesh in view of Yoo teach the semiconductor package of claim 1,
wherein the first semiconductor chip (1, fig 5) [Derakhshandesh , 0033] includes a first wiring structure (top 5-BEOL and 4-FEOL, shown in fig 2B) [0033] and the second semiconductor chip (20, fig 5) [Derakhshandesh, 0033] includes a second wiring structure (5 and 4, fig 5)
wherein the first and second wiring structures (top and bottom BEOL/FEOL are electrically connected to the first bump structure (10/6, fig 5) [Derakhshandesh,0031 0033] , and
wherein the first and second wiring structures are electrically insulated [0033] from the second bump structure (11/12 dummy structure, fig.5) [Derakhshandesh,0033].
Re claim 11 Derakhshandesh teach a semiconductor package comprising:
a first semiconductor chip (1, fig 5),
wherein the first semiconductor chip (1, fig 5)[0046] extends in each of first (x-axis) and second directions (z-axis) that intersect each other;
a second semiconductor chip (20, fig 5) [0046] stacked on the first semiconductor chip (1, fig 5 )[0046] in a third direction (y-axis) perpendicular to each of the first (x-axis) and second directions (z-axis),
wherein the second semiconductor chip (20, fig 5) includes a first area (middle area) and a second area (corner area, fig 5) that is adjacent to and extends around the first area (around middle area);
a bump structure (10/6 and 11/12, fig 5) [0046] between the first (1, fig 5) and second semiconductor chips (20, fig 5) [0046] and
wherein the bump structure (10/6 and 13) includes: a connection bump structure (10/6, fig 5) overlapping the first area (middle area) in the third direction (y-axis) and electrically connected to the first (1, fig 5) and second semiconductor chips (20, fig 5); and
a dummy bump structure (11/12, fig 5) [0046] overlapping the second area (corner area, fig 5) in the third direction (y-axis) and electrically insulated [0033] from the first (1, fig 5) and second semiconductor chips (20, fig 5),
wherein the connection bump structure (10/6, fig 5) and the dummy bump structure (11/12, fig 5) are spaced apart from each other (see fig 5), and wherein a thickness of the dummy bump structure (11, fig 5) in the third direction (y-axis) is larger than a thickness of the connection bump structure (10/6, fig 5) [0046] in the third direction (y-direction).
Derakhshandesh a conductive material layer between the first and second semiconductor chips, wherein the conductive material surrounds a portion of the bump structure.
a conductive material layer (anisotropic conductive adhesive or an isotropic conductive adhesive-170, fig 1) [0031] between the first and second semiconductor chips (between 131 and 133, fig 1) [0031], wherein the conductive material (170, fig 1) surrounds a portion of the bump structure ( 116/141, fig 1) [0016 0026].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yoo into the structure of Derakhshandesh to include a conductive material layer between the first and second semiconductor chips, wherein the conductive material surrounds a portion of the bump structure as claimed.
The ordinary artisan would have been motivated to modify Derakhshandesh based in teaching Yoo in the above manner for the purpose of improving reliability of the device [0034].
Re claim 12. Derakhshandesh in view of Yoo teach the semiconductor package of claim 11, wherein a maximum width of the dummy bump structure (11/12, fig 5) [Derakhshandesh, 0046] in the first direction (x-axis) is larger than a maximum width of the connection bump structure (10/6, fig 5) [0046] in the first direction (x-axis) [Derakhshandesh ,0046].
Re claim 13 Derakhshandesh in view of Yoo teach the semiconductor package of claim 11, wherein the dummy bump structure(11/12, fig 5) includes a first solder bump (11, fig 5) [Derakhshandesh , 0033] between a first-first wiring pad (bottom 12, fig 5) [0033] on the first semiconductor chip (1, fig 5) and a first- second (top 12, fig 5) wiring pad on the second semiconductor chip (20, fig 5) [Derakhshandesh, 0033],
wherein the connection bump structure (10/6, fig 5) includes a second solder bump (10, fig 5) [Derakhshandesh , 0033] between a second-first wiring pad (bottom 6, fig 5) [0033] on the first semiconductor chip (1, fig 5) and a second-second wiring pad (top 6, fig 5) [Derakhshandesh ,0033] on the second semiconductor chip (20, fig 5), and
wherein the first-first wiring pad (bottom 12, fig 5) [Derakhshandesh, 0033] on the first semiconductor chip (1, fig 5) [Derakhshandesh , 0033] includes a plurality of first-first wiring sub-pads (bottom left 12 and right 12, fig 5) spaced apart from each other (see fig 5) [Derakhshandesh, 0033] .
Re claim 14 Derakhshandesh in view of Yoo teach the semiconductor package of claim 13, wherein the first solder bump (11, fig 5) [00033] is between the first-first wiring sub-pads (bottom left and right 12, fig 5) [Derakhshandesh, 0033] that are spaced apart from each other in the first direction (x-axis, fig 5) [Derakhshandesh, 0033].
Re claim 15 Derakhshandesh in view of Yoo teach the semiconductor package of claim 13, wherein a thickness of the first solder bump (thickness of 11, fig 5) [0033] in the third direction (y-axis) is larger than a thickness of the second solder bump (thickness of 10, fig 5) in the third direction (y-axis)
Re claim 16 Derakhshandesh in view of Yoo the semiconductor package of claim 11, wherein the conductive material layer (170 , fig 1) [Yoo, 0031] includes a resin layer (polymer resin, thermosetting resin, a thermo-plastic resin,) [Yoo, 0031] and a filler (conductive particles comprise Ni, Au, Ag, or Cu in the resin layer (fig 1) [Yoo 0031].
Re claim 18. A semiconductor package (fig 5) [0033,0046] comprising:
a substrate (2, fig 5) [0033] wherein the substrate (2, fig 5) [0033] extends in each of first ( x-axis) and second directions (z-axis) that intersect each other;
a first semiconductor chip (1, fig 5) [0033] stacked on the substrate (2, fig 5) in a third direction (y-axis) perpendicular to each of the first (x-axis) and second directions (z-axis);
a second semiconductor chip (20, fig 5) stacked on the first semiconductor chip (1, fig 5) in the third direction (y-axis), wherein the second semiconductor chip (20, fig 5) includes a first area (middle area) and a second area (corner area) that is adjacent to and extends around the first area (corner area surrounds middle area, fig 5) ;
a bump structure (10/6, 11/12, fig 5) [0033] that is configured to bond the first semiconductor chip (1, fig 5) [0033] and the second semiconductor chip (20, fig 5) [0033] to each other between the first semiconductor chip (1, fig 5) and the second semiconductor chip (20, fig 5) [0033]; and
wherein the first semiconductor chip (1, fig 5) [0033] includes a through-via extending (15, fig 5) [0046] through at least a portion (middle portion of 1, fig 5) of the first semiconductor chip (1, fig 5), wherein the through-via electrically connects the second semiconductor chip (20, fig 5) [0046] and the substrate (2, fig 5) [0046-0047] to each other,
wherein the bump structure (10/6, 11/12, fig 5) [0033] includes a first bump structure (10/6, fig 5) overlapping the first area (middle area, fig 5) [0033] in the third direction (y-axis), and a second bump structure (11/12, fig 5) [0046, 0047] overlapping the second area (corner area, fig 5) in the third direction (y-axis), and
wherein a thickness of the first bump structure (10/6, fig 5) in the third direction (y-axis) is different (smaller) from a thickness of the second bump structure (11/12, fig 5) [0033] in the third direction (y-axis).
Derakhshandesh does not teach a conductive material layer between and second semiconductor chips, wherein the conductive material surrounds a portion of the bump structure.
Yoo teaches a conductive material layer (170, fig 1) [0031] between and second semiconductor chips (between 131 and 133, fig 1), wherein the conductive material (170, fig 1) [00131] surrounds a portion (around 141 and 116) of the bump structure (141/116, fig 1) [0016/0026].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yoo into the structure of Derakhshandesh to include a conductive material layer between and second semiconductor chips, wherein the conductive material surrounds a portion of the bump structure as claimed.
The ordinary artisan would have been motivated to modify Derakhshandesh based in teaching Yoo in the above manner for the purpose of improving the reliability of the device [0034].
Re claim 19. Derakhshandesh in view of Yoo teach the semiconductor package of claim 18, wherein the thickness (top to bottom) of the second bump structure (11/12, fig 5) [Derakhshandesh, 0033] in the third direction (y-axis) is larger (11 is thicker than 10) than the thickness of the first bump structure (10/6, fig 5) in the third direction (y-axis), and
wherein a width (left to right) of the second bump structure (11/12, fig 5) in [Derakhshandesh , 0033] the first direction is greater than a width of the first bump structure (10/6) in the first direction(x-axis, see fig 5) [Derakhshandesh, 0033].
Re claim 20 Derakhshandesh in view of Yoo teach the semiconductor package of claim 18, wherein the first bump structure (10/6, fig 5) [Derakhshandesh 0033] is electrically connected to the first and second semiconductor chips, and
wherein the second bump structure (11/12, fig 5) [0033] is electrically insulated from the first (1, fig 5) [0033] and second semiconductor chips (20, fig 5) [Derakhshandesh 0046].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Derakhshandesh modified by Yoo as applied to claim 1 and further in view of Seo-1 et al (US 20170084558 A1).
Re claim 5. Derakhshandesh in view of Yoo teach the semiconductor package of claim 4,
Derakhshandesh and Yoo do not tach each of the plurality of second-first wiring sub-pads has an elliptical shape or a circular shape in a plan view of the semiconductor package.
Seo-1 teaches each of the plurality of second-first wiring sub-pads (left and right 110p, fig 3) [0049] has an elliptical shape or a circular shape (elliptical or circular shape, fig 3) [0049] in a plan view of the semiconductor package (fig 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Seo-1 into the structure of Derakhshandesh to include each of the plurality of second-first wiring sub-pads has an elliptical shape or a circular shape in a plan view of the semiconductor package as claimed.
The ordinary artisan would have been motivated to modify Derakhshandesh and Yoo based on the teaching of Seo-1 in the above manner in order to resist electrical or mechanical stress [0048].
Further, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Derakhshandesh modified by Yoo as applied to claim 1 and further in view of Seo et al (US 20170338206 A1).
Re claim 10 Derakhshandesh in view of Yoo teach the semiconductor package of claim 1,
Derakhshandesh and Yoo do not teach a plurality of semiconductor chips on the first and second semiconductor chips and electrically connected to each other via a through-via.
Seo does teach a plurality of semiconductor chips (C3, C4, fig 7) [0026] on the first (C1, fig 7) [0026] and second semiconductor chips (C2, fig 7) [0026] and electrically connected to each other via a through-via (116, fig 7) [0036].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of to include as claimed.
The ordinary artisan would have been motivated to modify Derakhshandesh and Yoo based on the teaching of Seo in the above manner for the purpose of improving electrical performance of the package.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Derakhshandesh modified by Yoo as applied to claim 11, further in view of Watanable et al (US 20180226362A1).
Re claim 17 Derakhshandesh in view of Yoo teach the semiconductor package of claim 11,
Derakhshandesh and Yoo do not teach a plurality of alignment patterns in the first area in a plan view of the semiconductor package.
Watanable does teach a plurality of alignment patterns (AM4, fig 13) [0162, fig 13] in the first area (area of AM, fig 13)[0162, fig 13] in a plan view of the semiconductor package (fig 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Watanable into the structure of Derakhshandesh and Yoo to include as claimed.
The ordinary artisan would have been Derakhshandesh and Yoo based on the teaching of Watanable in the above manner for the purpose of achieving high accuracy alignment [0162].
Conclusion
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/8/26