Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/13/2023 and 03/05/2025 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. US 10, 10505020 and in further view of Frougier et al, US 20200287046 A1.
Liu teaches:
"A semiconductor device, comprising:
a substrate comprising a p-type well (figure 8, see element "P-WELL"),
an n-type well (Figure 8, see element "P-WELL"), and a depletion region (see above discussion), the depletion region being disposed between the p-type well and the n-type well;
a first epitaxial layer (figure 8, see element 805a);
a second epitaxial layer (figure 8, see element 805c) disposed on the n-type
well; and
a gate formed (figure 8, see element 810) around a channel (figure 8,
see element 825a) and between the first epitaxial layer (figure 8, see
element 805a) and the second epitaxial layer (figure 8, see element 805c)".
Note: a depletion region is an implicit feature of any pn-junction.
Moreover, a width of a depletion region can varies depending on a bias of said
junction. When the pn-junction is forward-biased, the external voltage reduces
the built-in potential barrier and the depletion region becomes narrower.
Conversely, when the pn-junction is reverse-biased: the external voltage
increases the built-in potential barrier and the depletion region becomes wider.
Liu fails to teach: the second epitaxial layer is also disposed on the depletion region; and an insulating layer is disposed on the p-type well, and the first epitaxial layer is
disposed thereon.
Frougier discloses a bottom isolation regions 402 which are
provided for finFET and/or nanosheet devices. (figure 4)
Even though Liu does not explicitly disclose a depletion region. This region is however implicitly disclosed and disposed at a boundary (junction) between the p-well and n-well.
Therefore, It would be obvious for the person skilled in the art prior to the effective filing date of the claimed invention to provide a region 805c sufficiently close to the aforementioned junction, because an electrical isolation is formed by a pn- junction between the p-well and the source region 805a. (Liu)
In regards to claim 10,
Liu teaches:
"A semiconductor device, comprising:
a substrate comprising a p-type well (figure 8, see element "P-WELL"),
an n-type well (Figure 8, see element "P-WELL"), and a depletion region (see above discussion), the depletion region being disposed between the p-type well and the n-type well;
a first epitaxial layer (figure 8, see element 805a);
a second epitaxial layer (figure 8, see element 805c); and
a gate formed (figure 8, see element 810) around a channel (figure 8,
see element 825a) and between the first epitaxial layer (figure 8, see
element 805a) and the second epitaxial layer (figure 8, see element 805c)".
note: a depletion region is an implicit feature of any pn-junction.
Moreover, a width of a depletion region can varies depending on a bias of said
junction. When the pn-junction is forward-biased, the external voltage reduces
the built-in potential barrier and the depletion region becomes narrower.
Conversely, when the pn-junction is reverse-biased: the external voltage
increases the built-in potential barrier and the depletion region becomes wider.
Liu fails to teach: the second epitaxial layer is also disposed on the depletion region; and an insulating layer is disposed on the p-type well, and the first epitaxial layer is
disposed thereon.
Frougier discloses a bottom isolation regions 402 which are
provided for finFET and/or nanosheet devices. (figure 4)
Even though Liu does not explicitly disclose a depletion region. This region is however implicitly disclosed and disposed at a boundary (junction) between the p-well and n-well.
Therefore, It would be obvious for the person skilled in the art prior to the effective filing date of the claimed invention to provide a region 805c sufficiently close to the aforementioned junction, because an electrical isolation is formed by a pn- junction between the p-well and the source region 805a. (Liu)
In regards to claims 2 and 3, and 11 and 12,
Liu teaches see column 7, line 18 - line 29: "For P-type LDMOS structures, the raised source/ drain EPI material is changed from N-type to P-type and the gate materials correspond to standard P-type gate materials. In addition, the P-wells are swapped with N-wells, and the N-wells are swapped with P-wells".
In regards to claims 5 and 13,
Liu discloses an isolation structure (808) Figure 8.
In regards to the dimensions, these values would have been optimized through routine experimentation and would not lend themselves to patentability, in the instant application without displaying unexpected results. (in Re Aller)
Furthermore in regards to claims 6-8 and 14, in regards to the dimensions, these values would have been optimized through routine experimentation and would not lend themselves to patentability, in the instant application without displaying unexpected results. (in Re Aller)
In regards to 9 and 15,
Frougier teaches: wherein the gate comprises polysilicon (para 94) and the channel comprises a silicon nanosheet (para 37).
Claim(s) 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. US 10, 10505020 in view of Frougier et al, US 20200287046 A1 and in further view of Shrivastava et al, US 2014/0145625 A1.
Liu teaches:
"A semiconductor device, comprising:
a substrate comprising a p-type well (figure 8, see element "P-WELL"),
an n-type well (Figure 8, see element "P-WELL"), and a depletion region (see above discussion), the depletion region being disposed between the p-type well and the n-type well;
a first epitaxial layer (figure 8, see element 805a);
a second epitaxial layer (figure 8, see element 805c); and
a gate formed (figure 8, see element 810) around a channel (figure 8,
see element 825a) and between the first epitaxial layer (figure 8, see
element 805a) and the third epitaxial layer (figure 8, see element 805c)".
Note: a depletion region is an implicit feature of any pn-junction.
Moreover, a width of a depletion region can varies depending on a bias of said
junction. When the pn-junction is forward-biased, the external voltage reduces
the built-in potential barrier and the depletion region becomes narrower.
Conversely, when the pn-junction is reverse-biased: the external voltage
increases the built-in potential barrier and the depletion region becomes wider.
Liu fails to teach: a first insulating layer is disposed on the p-type well, and the first epitaxial layer is disposed thereon. the third epitaxial layer is disposed on the depletion region; and
a second insulating layer is provided and a second epitaxial layer is provided
thereon the second epitaxial layer is also disposed on the depletion region;
the first gate is formed between the first epitaxial layer and the second epitaxial layer; and a second gate is formed around the channel and between the second epitaxial layer and the third epitaxial layer.
Frougier discloses a bottom isolation regions 402 which are
provided for finFET and/or nanosheet devices. (figure 4)
Even though Liu does not explicitly disclose a depletion region. This region is however implicitly disclosed and disposed at a boundary (junction) between the p-well and n-well.
Shrivastava teaches: a split-gate structure, in which the channel region is effectively divided, a potential difference between the drain contact and the drain/channel junction is reduced, and thereby it allows the switching of high drain voltages (figure 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the above references, because it thereby improve the high voltage capability by using a multi-dimension approach without substantially increasing the drain resistance. In particular, embodiments of the invention use a multi-dimensional approach to reduce the high potential difference between the drain contact and the drain/channel junction, and thereby allow the switching of high drain voltages (para 35, Shrivastava)
In regards to claims 17 and 18,
Liu teaches see column 7, line 18 - line 29: "For P-type LDMOS structures, the raised source/ drain EPI material is changed from N-type to P-type and the gate materials correspond to standard P-type gate materials. In addition, the P-wells are swapped with N-wells, and the N-wells are swapped with P-wells".
In regards to claim 19,
Liu discloses an isolation structure (808) Figure 8.
In regards to the dimensions, these values would have been optimized through routine experimentation and would not lend themselves to patentability, in the instant application without displaying unexpected results. (in Re Aller)
Furthermore in regards to claim 20, in regards to the dimensions, these values would have been optimized through routine experimentation and would not lend themselves to patentability, in the instant application without displaying unexpected results. (in Re Aller)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893