DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on March 10th, 2026, has been entered.
Upon entrance of the Amendment, claims 2, 3, and 11 were amended. Claims 1-11 are currently pending.
Claim 11 was rejected under 35 U.S.C. l 12(b) as being indefinite. Claim 11 has been amended. The rejections of claim 11 under 35 U.S.C. l 12(b) has been overcome and is withdrawn.
Response to Arguments
Applicant's arguments filed on March 10th, 2026 have been fully considered but they are not persuasive.
The Applicant has argued “… Cheng discloses that the nanowires 60 function as the seed for the epitaxial growth of the epitaxy 120. Thus, layer 110, which the Examiner equates with the claimed "sacrificial layer," does not function as the seed layer for the epitaxial growth of the epitaxy 120…” The argument is not persuasive because the claim does not require the sacrificial layer function as a seed layer for growing the source/drain. The claim recites “the sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor”. Since the prior art discloses the sacrificial layer is located right beneath the source/drain regions of the upper field-effect transistor regions, the limitation of “the sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor” is satisfied.
The Applicant has argued “… FIG. 17 depicts an isometric view of semiconductor structure 10 at an intermediate stage of semiconductor device fabrication" in which "fabrication layer 130 is formed" and "FIG. 18 depicts structure 10 ... with layer 130 and layer 110 or the combined layer 130 removed." Accordingly, Cheng discloses that the layer 130, which the Examiner equates with the claimed "oxide layer," is removed during fabrication. Thus, Cheng fails to disclose an oxide layer separating the source/drain regions of the lower field-effect transistor from the source/drain regions of the upper field-effect transistor.” The argument is not persuasive because Fig. 17 was cited for meeting the requirements of claim 8. In Fig. 17, oxide 130 are still present between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor. Since the source/drain regions is not seen the in Fig. 17 (because they are covered by the oxide), Fig. 18 was provided just as illustration for seeing the source/drain regions through the oxide. Since the claim depicts a structure, a structure disclosed by the prior art during fabrication process could be used for rejections, as long as it meets all limitations of the claim. The cited structure doesn’t have to be a final product.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is ejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the silicon-germanium is SixGe1-x. There is insufficient antecedent basis for “the silicon-germanium” in the claim. For the purpose of compact prosecution, the Examiner assumes claim 3 is dependent from claim 2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-9 and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rachmady et al, (U.S. Patent Application Publication No. 2020/0212038).
Regarding to claim 8, Rachmady teaches a three-dimensional field-effect transistor comprising:
a lower field-effect transistor comprising a source region, a drain region, a channel region between the source region and the drain region, and a gate on the channel (Fig. 5K, lower field-effect transistor comprising source region 306/left, drain region 306/right, channel region 508 between the source region and the drain region, and gate 304 on the channel);
an upper field-effect transistor stacked on the lower field-effect transistor (Fig. 5K, the upper field-effect transistor having S/D regions 308).
wherein each of the lower field-effect transistor and the upper field-effect transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate on the channel (Fig. 5K, lower field-effect transistor comprising source region 306/left, drain region 306/right, channel region 508 between the source region and the drain region, and gate 304 on the channel; upper field-effect transistor comprising source region 308/left, drain region 308/right, channel region 510 between the source region and the drain region, and gate 304 on the channel), and
wherein the source region and the drain region of the lower field-effect transistor are separated from the source region and the drain region of the upper field-effect transistor by an oxide layer (Fig. 5K, element 516; [0040], lines 6-7).
Regarding to claim 9, Rachmady teaches the lower field-effect transistor is an n-type field-effect transistor ([0040], line 5) and the upper field-effect transistor is a p-type field-effect transistor ([0040], line 10).
Regarding to claim 11, Rachmady teaches a thickness of the sacrificial layer is less than a thickness of each of the source/drain regions of the upper field-effect transistor and the source/drain regions of the lower field-effect transistor (Fig. 5K).
Claims 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (U.S. Patent No. 9,224,811) (Fig. 17 is being cited for the rejections. Fig. 18 is just for illustration purpose, in which the contents inside the cover are showed).
Regarding to claim 8, Cheng teaches a three-dimensional field-effect transistor (Fig. 17) comprising:
a lower field-effect transistor comprising a source region, a drain region, a channel region between the source region and the drain region, and a gate on the channel (Figs. 17-18, field-effect transistor comprising source region 100/left, drain region 100/right, channel region 62 between the source region and the drain region, and gate 50 on the channel);
an upper field-effect transistor stacked on the lower field-effect transistor (Figs. 17-18, the upper field-effect transistor having S/D regions 120).
wherein each of the lower field-effect transistor and the upper field-effect transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate on the channel (Figs. 17-18, lower field-effect transistor comprising source region 100/left, drain region 100/right, channel region 62 between the source region and the drain region, and gate 50 on the channel; upper field-effect transistor comprising source region 120/left, drain region 120/right, channel region 61 between the source region and the drain region, and gate 50 on the channel), and
wherein the source region and the drain region of the lower field-effect transistor are separated from the source region and the drain region of the upper field-effect transistor by an oxide layer (Fig. 17, oxide 130 separated the source region and the drain region of the lower field-effect transistor from the source region and the drain region of the upper field-effect transistor. Please see Fig. 18 as illustration of S/D regions as being looked through the oxide cover).
Regarding to claim 9, Cheng teaches the lower field-effect transistor is an n-type field-effect transistor (column 13, line 7, S/D layer 100 is phosphorus doped, in other words, it is n-type) and the upper field-effect transistor is an p-type field-effect transistor (column 13, line 64, S/D layer 120 is boron doped, in other words, it is p-type).
Regarding to claim 10, Cheng teaches the lower field-effect transistor is a p-type field-effect transistor (column 13, line 6, S/D layer 100 is boron doped, in other words, it is p-type) and the upper field-effect transistor is an n-type field-effect transistor (column 13, line 65, S/D layer 120 is phosphorus doped, in other words, it is n-type).
Regarding to claim 11, Cheng teaches a thickness of the sacrificial layer is less than a thickness of each of the source/drain regions of the upper field-effect transistor and the source/drain regions of the lower field-effect transistor (Fig. 17).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (U.S. Patent No. 9,224,811).
Regarding to claim 1, Cheng teaches a method of manufacturing a three-dimensional field-effect transistor including an upper field-effect transistor stacked on a lower field-effect transistor, the method comprising (the method steps are not claimed to impart in a specific order):
epitaxially growing source/drain regions of the lower field-effect effect transistor (Fig. 13, element 100, column 12, lines 31-32);
growing a sacrificial layer on an upper surface of the source/drain regions of the lower field-effect transistor (Fig. 14, element 110, column 13, lines 22-23);
epitaxially growing source/drain regions of the upper field-effect transistor on the sacrificial layer, wherein the sacrificial layer is a seed layer for the source/drain regions of the upper field-effect transistor (Fig. 16, element 120, column 13, lines 58-59);
etching the sacrificial layer to form a gap between the source/drain regions of the lower field-effect transistor and the source/drain regions of the upper field-effect transistor (Fig. 18); and
depositing an oxide layer in the gap (Fig. 17, element 130; column 14, line 6).
Cheng does not disclose the etching the sacrificial layer is selective. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cheng to make the process of etching the sacrificial layer to be selective in order to prevent damaging the epitaxial stack, thus to increase reliability.
Regarding to claim 4, Cheng teaches a thickness of the sacrificial layer is less than a thickness of each of the source/drain regions of the upper field-effect transistor and the source/drain regions of the lower field-effect transistor (Fig. 18).
Regarding to claim 5, Cheng teaches a thickness of the oxide layer is less than a thickness of each of the source/drain regions of the upper field-effect transistor and the source/drain regions of the lower field-effect transistor (Fig. 18, the thickness of the gap, where the oxide to be formed in, is less than the thickness of S/D 100 or S/D 120).
Regarding to claim 6, Cheng teaches the lower field-effect transistor is an n-type field-effect transistor (column 13, line 7, S/D layer 100 is phosphorus doped, in other words, it is n-type) and the upper field-effect transistor is an p-type field-effect transistor (column 13, line 64, S/D layer 120 is boron doped, in other words, it is p-type).
Regarding to claim 7, Cheng teaches the lower field-effect transistor is a p-type field-effect transistor (column 13, line 6, S/D layer 100 is boron doped, in other words, it is p-type) and the upper field-effect transistor is an n-type field-effect transistor (column 13, line 65, S/D layer 120 is phosphorus doped, in other words, it is n-type).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Rachmady et al. (U.S. Patent Application Publication No. 2020/0212038), as applied to claim 8 above, in view of Cheng et al. (U.S. Patent No. 9,224,811).
Regarding to claim 10, Rachmady does not disclose the lower field-effect transistor is a p-type field-effect transistor and the upper field-effect transistor is an n-type field-effect transistor. Cheng discloses the lower field-effect transistor is a p-type field-effect transistor (column 13, line 6, S/D layer 100 is boron doped, in other words, it is p-type) and the upper field-effect transistor is an n-type field-effect transistor (column 13, line 65, S/D layer 120 is phosphorus doped, in other words, it is n-type). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rachmady in view of Cheng to configure the lower field-effect transistor to be a p-type field-effect transistor and the upper field-effect transistor to be an n-type field-effect transistor in order to make the structure useful for a desired application.
Allowable Subject Matter
Claim 2 is allowed.
Claim 2 has been rewritten in independent form including all of the limitations of the base claim. The reasons for allowance of claim 2 were indicated in the previous Office Action.
The rejection of claim 1 would be overcome if the claim is amended as “the sacrificial layer functions as a seed layer for the epitaxially growing of the source/drain regions of the upper field-effect transistor”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
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