DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/1 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
7. Claim(s) 1, 10, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii et al. (US 2018/0301509 A1, hereafter Ishii) in view of Tsuchiya (US 2011/0147889 A1).
Regarding claim 1, in Fig. 7 Ishii teaches image sensor (600, [0095]) comprising:
a semiconductor substrate (100, [0030]) comprising a first surface (see annotated Fig. 7), a second surface (see annotated Fig. 7), and a photoelectric conversion region (110, [0101]);
a buried gate structure (TGE, [0107]) disposed in a buried gate trench (see annotated Fig. 7) and extending into the semiconductor substrate (100) from the first surface of the semiconductor substrate;
a floating diffusion region (631, [0111]) disposed on one side of the buried gate structure (TGE) in the semiconductor substrate (100); and
a contact (BCP1, [0049]) extending in a vertical direction perpendicular to the first surface of the semiconductor substrate (100).
Ishii fails to disclose a contact pad disposed on the first surface of the semiconductor substrate (100) above the floating diffusion region (631) and comprising polysilicon and an intermediate layer disposed on the contact pad and comprising a metal silicide.
However, Tsuchiya teaches in Fig. 23B a device in which a polysilicon contact pad (38a, [0125]) and metal silicide layer (39a, [0125]) are formed above a diffusion region. The contact pad is used to increase the overlap margin, and the silicide is added to lower contact resistance [0090]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the image sensor of Ishii to include the contact pad and silicide layer of Tsuchiya in order to get the expected result of electrical contact between the floating diffusion region and the contact.
PNG
media_image1.png
685
955
media_image1.png
Greyscale
Regarding claim 10, Ishii in view of Tsuchiya teach the image sensor of claim 1. Ishii further teaches a low-doping region (135, [0038]) disposed between the floating diffusion region (631, [0111]) and the buried gate structure (TGE, [0107]) and around the floating diffusion region (631) in the semiconductor substrate (100, [0030]),
wherein the floating diffusion region (631) comprises a first type of impurity having a first type of impurity concentration [0044] and the low-doping region (135) comprises a first type of impurity having a second type of impurity concentration lower than the first type of impurity concentration.
The low doping region 135 is taught to have a lower concentration than floating diffusion region 131 [0044], which is taught to be the same as floating diffusion region 631 [0111].
Regarding claim 13, Ishii in view of Tsuchiya teach the image sensor of claim 1. Ishii further teaches a pixel separation structure (141/143, [0047]) disposed in a pixel trench passing through the semiconductor substrate 100, [0030]); a planar gate structure (see annotated Fig. 7) disposed on the first surface of the semiconductor substrate (see annotated Fig. 7); and a color filter (CF1, [0071]) disposed on the second surface of the semiconductor substrate (see annotated Fig. 7).
PNG
media_image1.png
685
955
media_image1.png
Greyscale
8. Claim(s) 2-3, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii in view of Tsuchiya, and in further view of Lee et al. (US 2005/0218476 A1, hereafter Lee).
Regarding claim 2, Ishii in view of Tsuchiya teach the image sensor of claim 1. Ishii in view of Tsuchiya fail to teach an etch stop layer disposed on the first surface of the semiconductor substrate and covering an upper surface of the buried gate structure, wherein the etch stop layer surrounds a side wall of the contact pad.
However, Lee teaches an integrated process in an etch stop layer (18, [0039]) is deposited over the entirety of exposes surfaces (which would include covering the buried gate structure of Ishii). This deposition is done before an etching step in Fig. 4 and creation of the contact pad (22 of Fig. 6, [0043]). The result in Fig. 6 is a contact pad with the etch stop layer surrounding the side wall of the contact pad. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ishii in view of Tsuchiya to deposit an etch stop layer as Lee does in order to form the contact pad.
Regarding claim 3, Ishii in view of Tsuchiya teach the image sensor of claim 2. Lee further shows in Fig. 6 the contact pad (22 of Fig. 6, [0043]) has an upper surface disposed at a higher level than an upper surface of the etch stop layer (18, [0039]).
Regarding claim 20, in Fig. 7 Ishii teaches image sensor (600, [0095]) comprising:
a semiconductor substrate (100, [0030]) comprising a first surface (see annotated Fig. 7) and a second surface (see annotated Fig. 7), and further comprising a photoelectric conversion region (110, [0101]);
a pixel separation structure (141/143, [0047]) disposed in a pixel trench passing through the semiconductor substrate (100) to define a plurality of pixels;
a buried gate structure (TGE, [0107]) disposed in a buried gate trench (see annotated Fig. 7) extending into the semiconductor substrate (100) from the first surface of the semiconductor substrate (100);
a floating diffusion region (631, [0111]) comprising a first type of impurity (N-type doping in [0038]) and disposed on one side of the buried gate structure (TGE) in the semiconductor substrate (100);
a low-doping region (135, [0038]) comprising the first type of impurity and disposed between the floating diffusion region (631) and the buried gate structure (TGE) and disposed around the floating diffusion region in the semiconductor substrate; and
a contact (BCP1, [0049]) extending in a vertical direction perpendicular to the first surface of the semiconductor substrate (100).
Ishii fails to disclose a contact pad disposed on the first surface of the semiconductor substrate (100) above the floating diffusion region (631) and comprising polysilicon and an intermediate layer disposed on the contact pad and comprising a metal silicide.
However, in Fig. 2B Tsuchiya teaches in Fig. 23B a device in which a polysilicon contact pad (38a, [0125]) and metal silicide layer (39a, [0125]) are formed above a diffusion region. The contact pad is used to increase the overlap margin, and the silicide is added to lower contact resistance [0090]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the image sensor of Ishii to include the contact pad and silicide layer of Tsuchiya in order to get the expected result of electrical contact between the floating diffusion region and the contact.
Ishii in view of Tsuchiya fail to teach an etch stop layer disposed on the first surface of the semiconductor substrate and covering an upper surface of the buried gate structure, wherein the etch stop layer surrounds a side wall of the contact pad.
However, Lee teaches an integrated process in an etch stop layer (18, [0039]) is deposited over the entirety of exposes surfaces (which would include covering the buried gate structure of Ishii). This deposition is done before an etching step in Fig. 4 and creation of the contact pad (22 of Fig. 6, [0043]). The result in Fig. 6 is a contact pad with the etch stop layer surrounding the side wall of the contact pad. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ishii in view of Tsuchiya to deposit an etch stop layer as Lee does in order to form the contact pad.
PNG
media_image1.png
685
955
media_image1.png
Greyscale
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii in view of Tsuchiya as applied to claim 2 above, and in further view of Gehlen et al. (US 2022/0050506 A1, hereafter Gehlen).
Regarding claim 4, Ishii in view of Tsuchiya teach the image sensor of claim 1. Fig. 25B of Tsuchiya further discloses the contact pad (38a, [0125]) is disposed in a contact recess. While Tsuchiya does not teach a bottom surface of the contact pad is disposed at a lower level than the first surface of the semiconductor substrate, one of ordinary skill in the art would know to adjust the location of the contact pad to be embedded into the substrate as they are obvious variants of one another, as taught by Gehlen [0059]. Embedding the contact into the substrate would get the expected result of direct electrical connection between the contact and the floating diffusion region in Ishii.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishii in view of Tsuchiya as applied to claim 10 above, and in further view of Wang et. al (US 2021/0313448 A1).
Regarding claim 11, Ishii in view of Tsuchiya teach the image sensor of claim 10, wherein the floating diffusion region (631, [0111]) includes a first type impurity (N-type, [0038]), and the low-doping region (135, [0038]) includes the first type impurity [0044].
Ishii in view of Tsuchiya is silent on the exact dopants, only that they are of the N-type. However, one skilled in the art would know to use a reasonable N-type dopant, as taught to be known in the art by Wang where the first type (N-type) impurity includes at least one of phosphorus and arsenic [0038].
Regarding claim 12, Ishii in view of Tsuchiya teach the image sensor of claim 10, wherein the floating diffusion region (631, [0111]) includes a first type impurity (N-type, [0038]) and a second type of impurity, the low-doping region comprises the first type of impurity.
Ishii states that the floating diffusion region (131 which is structurally the same as 131 [0111]) is associated with the [first] conductivity type (N-Type) [0038], and not that the region solely contains these dopants. As this is in direct contact with the barrier dopant region 133 [0038] creating an N/P/N junction, diffusion of the dopants from the barrier dopant region into the floating diffusion region naturally occurs. Thus, the second type of impurity would also exist in the floating diffusion region.
Ishii in view of Tsuchiya is silent on the exact dopants for the first type and second type, only that they are of the N-type and P-type respectively. However, one skilled in the art would know to use a reasonable N-type or P-type dopant, as taught to be known in the art by Wang where the first type (N-type) impurity includes at least one of phosphorus and arsenic, and the second type of impurity (P-type) comprises germanium [0038].
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 5-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-20 of U.S. Patent No. 12,520,609 B1 in view of Tsuchiya.
For example, regarding independent claims 1, 14, and 20:
Present Application
U.S. Patent No. 12,520,609 B1
1) An image sensor comprising:
a semiconductor substrate comprising a first surface, a second surface, and a photoelectric conversion region;
a buried gate structure disposed in a buried gate trench and extending into the semiconductor substrate from the first surface of the semiconductor substrate;
a floating diffusion region disposed on one side of the buried gate structure in the semiconductor substrate;
a contact pad disposed on the first surface of the semiconductor substrate above the floating diffusion region and comprising polysilicon;
an intermediate layer disposed on the contact pad and comprising a metal silicide; and
a contact disposed on the intermediate layer and extending in a vertical direction perpendicular to the first surface of the semiconductor substrate.
1) An image sensor comprising:
a semiconductor substrate including a first surface and a second surface, and
further including a photoelectric conversion region;
a buried gate structure disposed in a buried gate trench extending into the semiconductor substrate from the first surface of the semiconductor substrate;
a floating diffusion region including a first type impurity and disposed on one side of the buried gate structure in the semiconductor substrate;
a contact disposed on the first surface of the semiconductor substrate above the floating diffusion region; and
a contact barrier region including a second type impurity and disposed between the contact and the floating diffusion region in the semiconductor substrate.
14) An image sensor comprising:
a semiconductor substrate comprising a first surface, a second surface, and a photoelectric conversion region;
a buried gate structure disposed in a buried gate trench and extending into the semiconductor substrate from the first surface of the semiconductor substrate;
a floating diffusion region comprising a first type of impurity and disposed on one side of the buried gate structure in the semiconductor substrate;
a contact disposed on the first surface of the semiconductor substrate above the floating diffusion region;
a contact pad disposed on the first surface of the semiconductor substrate above the floating diffusion region;
an intermediate layer disposed on the contact pad and comprising a metal silicide;
a contact disposed on the intermediate layer and extending in a vertical direction perpendicular to the first surface of the semiconductor substrate; and
a contact barrier region comprising a second type of impurity, different from the first type of impurity, and disposed under the contact pad and between the contact and the floating diffusion region.
14) An image sensor comprising:
a semiconductor substrate including a first surface and a second surface, and
further including a photoelectric conversion region;
a buried gate structure disposed in a buried gate trench and extending into the semiconductor substrate from the first surface of the semiconductor substrate;
a floating diffusion region including a first type impurity and disposed on one side of the buried gate structure in the semiconductor substrate;
a contact disposed on the first surface of the semiconductor substrate above the floating diffusion region; and
a contact barrier region including a second type impurity, different from the first type impurity, and disposed between the contact and the floating diffusion region in the semiconductor substrate.
20) An image sensor comprising:
a semiconductor substrate comprising a first surface and a second surface, and further comprising a photoelectric conversion region;
a pixel separation structure disposed in a pixel trench passing through the semiconductor substrate to define a plurality of pixels;
a buried gate structure disposed in a buried gate trench extending into the semiconductor substrate from the first surface of the semiconductor substrate;
a floating diffusion region comprising a first type of impurity and disposed on one side of the buried gate structure in the semiconductor substrate;
a low-doping region comprising the first type of impurity and disposed between the floating diffusion region and the buried gate structure and disposed around the floating diffusion region in the semiconductor substrate;
an etch stop layer disposed on the first surface of the semiconductor substrate and covering the buried gate structure;
a contact pad disposed to vertically overlap the floating diffusion region on the first surface of the semiconductor substrate and comprising a side wall surrounded by the etch stop layer;
an intermediate layer disposed on the contact pad and comprising a metal silicide;
a contact disposed on the intermediate layer and extending in a vertical direction perpendicular to the first surface of the semiconductor substrate; and
an interlayer insulating film disposed on the etch stop layer and surrounding the contact.
20) An image sensor comprising:
a semiconductor substrate including a first surface and a second surface, and
further including a photoelectric conversion region;
a pixel separation structure disposed in a pixel trench passing through the semiconductor substrate to define a plurality of pixels;
a buried gate structure disposed in a buried gate trench extending into the semiconductor substrate from the first surface of the semiconductor substrate;
a floating diffusion region including a first type impurity and disposed on one side of the buried gate structure in the semiconductor substrate;
a low-doping region including the first type impurity and disposed between the floating diffusion region and the buried gate structure and disposed around the floating diffusion region in the semiconductor substrate;
a contact disposed on the first surface of the semiconductor substrate above the floating diffusion region;
a contact barrier region including a second type impurity different from the first type impurity and disposed between the contact and the floating diffusion region in the semiconductor substrate; and
a barrier impurity region including the second type impurity and disposed in the semiconductor substrate to surround the floating diffusion region.
While U.S. Patent number 12,520,609 B1 fails to disclose an intermediate layer disposed on the contact pad and comprising a metal silicide and a contact disposed on the intermediate layer and extending in a vertical direction perpendicular to the first surface of the semiconductor substrate, Tsuchiya can be combined with U.S. Patent number 12,520,609 B1 to create the full device. Tsuchiya teaches in Fig. 23B a device in which a polysilicon contact pad (38a, [0125]) and metal silicide layer (39a, [0125]) are formed above a diffusion region. The contact pad is used to increase the overlap margin, and the silicide is added to lower contact resistance [0090]. Thus, it would have been obvious to one having ordinary skill in the art to modify the image sensor of U.S. Patent number 12,520,609 B1 to include the contact pad and silicide layer of Tsuchiya in order to get the expected result of electrical contact between the floating diffusion region and the contact.
Allowable Subject Matter
Claim(s) 14-19 would be allowed should the double patenting rejection be overcome.
The following is an examiner’s statement of reasons for allowance:
Claims 14-19 are allowable primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim(s) 14: “contact barrier region comprising a second type of impurity, different from the first type of impurity, and disposed under the contact pad and between the contact and the floating diffusion region”.
The closest prior art of record, Ishii teaches an image sensor with a diffusion region but fails to teach a contact barrier region with a second type of impurity, and disposed under a contact pad and between the contact and the floating diffusion region, nor could Examiner find any reason for this limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the double patenting rejection is overcome.
The following is a statement of reasons for the indication of allowable subject matter: Claims 5 is indicated as containing allowable subject matter as the prior art of record cannot anticipate or render obvious the following limitations: “a contact barrier region disposed under the contact pad”.
The closest prior art of record, Ishii teaches an image sensor with a diffusion region but fails to teach a contact barrier region with a second type of impurity, and disposed under a contact pad and between the contact and the floating diffusion region, nor could Examiner find any reason for this limitation.
Claims 6-9 are objected to by virtue of being ultimately dependent on objected claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892