DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 01/28/2026. Claims 1-30 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 01/11/2024 is acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/12/2025 and 02/10/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant’s election, without traverse invention I, Species II, directed to an embodiment as depicted in FIGS. [2A, 3], with claims 1-8, 11-13 and 25-30, in the “Response to Election / Restriction Filed” filed on 01/28/2026 is acknowledged.
This office action considers claims 1-30 pending for prosecution, wherein claims 9-10 and 14-24 are withdrawn from further consideration, and 1-8, 11-13 and 25-30 are presented for examination.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Mittal et al (US 2016/0334845 A1; hereafter lee) in view of Co et al (US 2015/0348928 A1; hereafter Co).
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Regarding claim 1. Mittal discloses an integrated circuit (IC) package (Fig 5), comprising:
a base structure (Fig 5, first substrate 220, Para [ 0038]);
an IC component (Fig 5, first die 222, Para [ 0038]) disposed on the base structure (first substrate 220);
a plurality of interposer connection structures (Fig 5, vias 510, Para [ 0054]) disposed on the base structure (Fig 5, first substrate 220, Para [ 0038]); and
an interposer structure (Fig 5, second substrate 240, Para [ 0044]) disposed over the IC component (Fig 5, first die 222, Para [ 0038]) and the plurality of interposer connection structures (Fig 5, vias 510, Para [ 0054]), wherein the plurality of interposer connection structures (Fig 5, vias 510, Para [ 0054]) is configured to connect the base structure (first substrate 220) and the interposer structure (Fig 5, second substrate 240, Para [ 0044]).
But Mittal does not disclose explicitly wherein each interposer connection structure of the plurality of interposer connection structures comprises:
a bond ball portion that is connected to the base structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the interposer structure, wherein a width of the bond ball portion is greater than a width of the bond wire portion.
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In a similar field of endeavor, Co discloses wherein each interposer connection (Fig 10, wire bonds 414, Para [ 0051]) structure of the plurality of interposer connection structures (Fig 10, wire bonds 414, Para [ 0051]) comprises:
a bond ball portion (conductive masses 520, Para [ 0044]) that is connected ( electrically connected) to the base structure ( substrate 504), and a bond wire portion (bases 416, Para [ 0049]) that is coupled to the bond ball portion (conductive masses 520, Para [ 0044]) and extends toward the interposer structure (redistribution layer 600, Para [ 0051]), wherein a width of the bond ball portion (conductive masses 520, Para [ 0044]) is greater than a width of the bond wire portion (bases 416, Para [ 0049]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Mittal in light of Co teaching “wherein each interposer connection (Fig 10, wire bonds 414, Para [ 0051]) structure of the plurality of interposer connection structures (Fig 10, wire bonds 414, Para [ 0051]) comprises:
a bond ball portion (conductive masses 520, Para [ 0044]) that is connected ( electrically connected) to the base structure ( substrate 504), and a bond wire portion (bases 416, Para [ 0049]) that is coupled to the bond ball portion (conductive masses 520, Para [ 0044]) and extends toward the interposer structure (redistribution layer 600, Para [ 0051]), wherein a width of the bond ball portion (conductive masses 520, Para [ 0044]) is greater than a width of the bond wire portion (bases 416, Para [ 0049])” for further advantage such as package protects a microelectronic element to avoid electrical short circuiting between the wire bonds so as to avoid malfunction or possible damage due to unintended electrical contact between the wire bonds and the microelectronic element.
Regarding claim 12. Mittal in light of Co discloses the IC package of claim 1, further comprising: Mittal further discloses a plurality of solder bumps or copper pillar bumps (solder 252, Para [ 0043]) under the base structure (first substrate 220) and configured for connecting the IC package to a circuit board (PCB).
Regarding claim 13. Mittal in light of Co discloses the IC package of claim 1, Mittal further discloses wherein: the IC component is an IC chip, or an assembly having a package substrate and the IC chip mounted on the package substrate (Fig 2, Para [ 0038-0045]).
ALTERNATE REJECTION:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-8, 11-13, 25-26 and 28-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato et al (US 2012/0280386 A1; hereafter Sato).
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Regarding claim 1. Sato discloses an integrated circuit (IC) package (Fig 6, Para [ 0084-0087]), comprising:
a base structure (Fig 6, lower substrate 412, Para [ 0084-0087]);
an IC component (microelectronic element 422, Para [ 0084-0087]) disposed on the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]);
a plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) disposed on the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]); and
an interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]) disposed over the IC component (microelectronic element 422, Para [ 0084-0087]) and the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]), wherein the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) is configured to connect the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]) and the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]), wherein each interposer connection (wire bonds 432, Para [ 0084-0087]) structure of the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) comprises:
a bond ball portion (bases 434, Para [ 0085]) that is connected (electrically connected) to the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]), and
a bond wire portion (wire bonds 432, Para [ 0084-0087]) that is coupled to the bond ball portion (bases 434, Para [ 0085]) and extends toward the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]), wherein a width of the bond ball portion (bases 434, Para [ 0085]) is greater than a width of the bond wire portion (wire bonds 432, Para [ 0084-0087]).
Regarding claim 2. Sato discloses the IC package of claim 1, Sato further discloses wherein: the bond ball portion (bases 434, Para [ 0085]) and the bond wire portion (wire bonds 432, Para [ 0084-0087]) of each one of the plurality of interposer connection structures comprise a metal (Para [ 0073]).
Regarding claim 3. Sato discloses the IC package of claim 2, Sato further discloses wherein: the metal comprises copper, aluminum, gold, or a combination thereof (Para [ 0073]).
Regarding claim 7 Sato discloses the IC package of claim 1, Sato further discloses wherein:
each interposer connection structure (wire bonds 432, Para [ 0084-0087]) of the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) further comprises a solder portion (solder 452) connecting an upper end of the corresponding bond wire portion (wire bonds 432, Para [ 0084-0087]) and the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]).
Regarding claim 8. Sato discloses the IC package of claim 1, Sato further discloses further comprising:
a molding compound (encapsulation layer 442, Para [ 0090]) portion between the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]) and the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]) and surrounding at least the bond ball portions (bases 434, Para [ 0085]) and a portion of the bond wire portions of the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]).
Regarding claim 11. Sato discloses the IC package of claim 1, Sato further discloses wherein: the base structure comprises a package substrate or a redistribution layer (Fig 6, lower substrate 412, Para [ 0084-0087]).
Regarding claim 12. Sato discloses the IC package of claim 1, Sato further discloses further comprising: a plurality of solder bumps or copper pillar bumps (solder 452, Para [ 0087]) under the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]) and configured for connecting the IC package to a circuit board (PCB 490).
Regarding claim 13. Sato discloses the IC package of claim 1, Sato further discloses wherein: the IC component is an IC chip, or an assembly having a package substrate and the IC chip mounted on the package substrate (Fig 6, Para [ 0085-0088]).
Regarding claim 25. Sato discloses an electronic device, comprising:
an integrated circuit (IC) package (Fig 6, Para [ 0084-0087]) that comprises:
a base structure (Fig 6, lower substrate 412, Para [ 0084-0087]);
an IC component (microelectronic element 422, Para [ 0084-0087]) disposed on the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]);
a plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) disposed on the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]); and
an interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]) disposed over the IC component (microelectronic element 422, Para [ 0084-0087]) and the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]), wherein the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) is configured to connect ( electrically connect) the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]) and the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]), and
wherein each interposer connection structure of the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) comprises:
a bond ball portion (bases 434, Para [ 0085]) that is connected to the base structure (Fig 6, lower substrate 412, Para [ 0084-0087]), and a bond wire portion (wire bonds 432, Para [ 0084-0087]) that is coupled to the bond ball portion (bases 434, Para [ 0085]) and extends toward the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]), wherein a width of the bond ball portion (bases 434, Para [ 0085]) is greater than a width of the bond wire portion (wire bonds 432, Para [ 0084-0087]).
Regarding claim 26. Sato discloses the electronic device of claim 25, Sato further discloses wherein: the bond ball portion (bases 434, Para [ 0085]) and the bond wire portion (wire bonds 432, Para [ 0084-0087]) of each one of the plurality of interposer connection structures comprise a metal, and the metal comprises copper, aluminum, gold, or a combination thereof (Para [ 0073]).
Regarding claim 28. Sato discloses the electronic device of claim 25, Sato further discloses
wherein: the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]) comprises a package substrate (Fig 6, upper substrate 412, Para [ 0084-0087]), and each interposer connection structure of the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) further comprises a solder portion (solder 452) connecting an upper end of the corresponding bond wire portion (wire bonds 432, Para [ 0084-0087]) and the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]).
Regarding claim 29. Sato discloses the electronic device of claim 25, Sato further discloses wherein: the interposer structure comprises a redistribution layer (Fig 6, upper substrate 412, Para [ 0084-0087]), and an upper end of the corresponding bond wire portion of each interposer connection structure (wire bonds 432, Para [ 0084-0087]) of the plurality of interposer connection structures (wire bonds 432, Para [ 0084-0087]) is connected to the interposer structure (Fig 6, upper substrate 412, Para [ 0084-0087]).
Regarding claim 30. Sato discloses the electronic device of claim 25, Sato further discloses wherein the electronic device comprises at least one of: a music player, a video player, an entertainment unit; a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle ( Para [ 0003-0010, 0110-0111]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al (US 2012/0280386 A1; hereafter Sato) as applied claims above and further in view of Fu et al (US 2015/01789590 A1; hereafter Fu).
Regarding claim 4. Sato discloses the IC package of claim 1, But Sato does not disclose explicitly wherein: the plurality of interposer connection structures has a pitch equal to or less than 150 micrometers (µm).
In a similar field of endeavor, Fu discloses wherein: the plurality of interposer connection structures has a pitch equal to or less than 150 micrometers (µm) (Para [ 0051, 0064]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Sato in light of Fu teaching “wherein: the plurality of interposer connection structures has a pitch equal to or less than 150 micrometers (µm) (Para [ 0051, 0064])” for further advantage such as provides interconnects with high aspect ratios and high density interconnection, which helps provide improved package performance, while keeping the package small and thin.
Regarding claim 5. Sato in light of Fu disclose the IC package of claim 4, Fu further disclose wherein: the plurality of interposer connection structures has the pitch equal to or less than 100 pm (Para [ 0051, 0064]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Sato in light of Fu teaching “wherein: the plurality of interposer connection structures has the pitch equal to or less than 100 pm (Para [ 0051, 0064])” for further advantage such as provides interconnects with high aspect ratios and high-density interconnection, which helps provide improved package performance, while keeping the package small and thin.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al (US 2012/0280386 A1; hereafter Sato) as applied claims above and further in view of KWAK (US 2022/0165651 A1; hereafter KWAK).
Regarding claim 6. Sato discloses the IC package of claim 1, But Sato does not disclose explicitly wherein: a distance between an upper surface of the base structure and a lower surface of the interposer structure is greater than 200 micrometers (µm).
In a similar field of endeavor, KWAK discloses wherein: a distance between an upper surface of the base structure and a lower surface of the interposer structure is greater than 200 micrometers (µm) (Para [ 0047]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Sato in light of KWAK teaching “wherein: a distance between an upper surface of the base structure and a lower surface of the interposer structure is greater than 200 micrometers (µm) (Para [ 0047])” for further advantage such as high- density interconnection with reduce packaging size.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al (US 2012/0280386 A1; hereafter Sato) as applied claims above and further in view of Fu et al (US 2015/01789590 A1; hereafter Fu) and KWAK (US 2022/0165651 A1; hereafter KWAK).
Regarding claim 27. Sato discloses the electronic device of claim 25, But Sato does not disclose explicitly wherein:
the plurality of interposer connection structures has a pitch equal to or less than 150 micrometers (µm), and a distance between an upper surface of the base structure and a lower surface of the interposer structure is greater than 200 (µm).
In a similar field of endeavor, Fu discloses wherein: the plurality of interposer connection structures has a pitch equal to or less than 150 micrometers (µm) (Para [ 0051, 0064]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Sato in light of Fu teaching “wherein: the plurality of interposer connection structures has a pitch equal to or less than 150 micrometers (µm) (Para [ 0051, 0064])” for further advantage such as provides interconnects with high aspect ratios and high density interconnection, which helps provide improved package performance, while keeping the package small and thin.
But Sato and Fu do not disclose explicitly a distance between an upper surface of the base structure and a lower surface of the interposer structure is greater than 200 µm.
In a similar field of endeavor, KWAK discloses wherein: a distance between an upper surface of the base structure and a lower surface of the interposer structure is greater than 200 micrometers µm (Para [ 0047]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to modify Sato and Fu in light of KWAK teaching “wherein: a distance between an upper surface of the base structure and a lower surface of the interposer structure is greater than 200 µm (Para [ 0047])” for further advantage such as high- density interconnection with reduce packaging size.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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