DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed May 4, 2026, in which: claim(s) 1, 2, 5, 17, 19, and 20 is/are amended; claim(s) 10-16 is/are cancelled; and the rejection of the claims are traversed. Claim(s) 1-9 and 17-20 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed May 4, 2026, with respect to the rejection(s) of amended claim(s) 1 and 17 and claims 2-9 and 18-20 which depends from claims 1 and 17 respectively their under 35 U.S.C. 103 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. There are many patents pertaining to forksheet transistor structures, so the title “Forksheet transistor structure and manufacturing thereof” is not specific as to the nature of the invention.
The following title is suggested: “Asymmetric forksheet transistor structure”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20230154847 A1, hereinafter Hsu), and further in view of Chen et al. (US 20240178128 A1, hereinafter Chen).
Regarding independent claim 1, Hsu discloses in Hsu FIG. 2F and FIG. 4 and associated text a semiconductor structure comprising: a first set of nanosheets having a first end and a second end (silicon layers 116a to 116c (FIG. 2F), which are divided amongst gates 108a to 108g (FIG. 4), specifically referring to those corresponding to gate 108e; the silicon layers are part of transistor 102, which may be a nanosheet transistor ([0034]), making these silicon layers nanosheets); a first conductive layer directly contacting the left sidewall of the dielectric bar, the first conductive layer surrounding the first set of nanosheets and covering the first end of the first set of nanosheets (gate 108e, which has the claimed structure, as shown in the figure below); and a second set of nanosheets and a second conductive layer, the second conductive layer directly contacting the right sidewall of the dielectric bar separating the second set of nanosheets from the right sidewall of the dielectric bar (gate 108d and corresponding silicon layers 116).
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Hsu does not explicitly disclose a dielectric bar having a left sidewall and a right sidewall or the second end of the first set of nanosheets directly contacting the left sidewall of the dielectric bar.
However, Hsu discloses an insulating material between gates 108 (particularly between 108e and 108d, corresponding to the first dielectric bar), which may be oxide ([0040]) and is a bar-like structure, as shown in the figure below. Additionally, the substrate 118 on which this material is formed is silicon ([0052]). Silicon oxide is well-known in the art to be a dielectric insulating material often disposed on silicon substates because its crystalline structure is similar to that of silicon, providing improved adhesion to the substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use silicon oxide as the insulating material disclosed by Hsu to have “a dielectric bar having a left sidewall and a right sidewall”, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Additionally, in the same field of endeavor, Chen discloses in Chen FIG. 24A and associated text the second end of the first set of nanosheets directly contacting the left sidewall of the dielectric bar (semiconductor layers 106a-106c directly contacting dielectric wall 119-1 as shown in region 153 in the mirrored and annotated Chen FIG. 24A below)
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Hsu with the forksheet transistor structure of Chen to provide a transistor with greater device density and scalability (Chen [0036]).
Regarding dependent claim 2, Hsu, as modified by Chen, further discloses in Hsu FIG. 4 and Chen FIG. 24A and associated text the dielectric bar is a first dielectric bar, further comprising a second dielectric bar, wherein the second dielectric bar has a left sidewall parallel to the right sidewall of the first dielectric bar (the bar-shaped insulating material between gates 108c and 108d, which is a dielectric bar, as interpreted above); the second set of nanosheets has a first end and a second end with the second end of the second set of nanosheets being directly contacting the left sidewall of the second dielectric bar (semiconductor layers 106a-106c directly contacting dielectric wall 119-1 as shown in region 153 in the mirrored and annotated Chen FIG. 24A above); and the second conductive layer directly contacts the left sidewall of the second dielectric bar; surrounds the second set of nanosheets; and covers the first end of the second set of nanosheets (as shown in the figure below).
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Regarding independent claim 17, Hsu discloses a semiconductor structure comprising: a first set of nanosheets having a first end and a second end, (silicon layers 116 within gate 108e, which are next to the insulating material); a first conductive layer surrounding the first set of nanosheets and directly contacting the left sidewall of the first dielectric bar (gate 108e, which has the claimed structure, as shown in the figure above); a second set of nanosheets having a first end and a second end (silicon layers 116 corresponding to gate 108d); and a second conductive layer surrounding the second set of nanosheets; directly contacting the left sidewall of the second dielectric bar; and separating the second set of nanosheets from the right sidewall of the first dielectric bar (gate 108d as shown in the figure above).
Hsu does not explicitly disclose a first and a second dielectric bar each having a left sidewall and a right sidewall, the second end of the first set of nanosheets directly contacting the left sidewall of the first dielectric bar, or the second end of the second set of nanosheets directly contacting the left sidewall of the second dielectric bar.
However, Hsu discloses an insulating material between gates 108 (particularly between 108e and 108d, corresponding to the first dielectric bar, and between 108d and 108c, corresponding to the second dielectric bar), which may be oxide ([0040]) and is a bar-like structure, as shown in the figure above. Additionally, the substrate 118 on which this material is formed is silicon ([0052]). Silicon oxide is well-known in the art to be a dielectric insulating material often disposed on silicon substates because its crystalline structure is similar to that of silicon, providing improved adhesion to the substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use silicon oxide as the insulating material disclosed by Hsu to have “a first and a second dielectric bar each having a left sidewall and a right sidewall”, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Additionally, in the same field of endeavor, Chen discloses in Chen FIG. 24A and associated text the second end of the first set of nanosheets directly contacting the left sidewall of the dielectric bar (semiconductor layers 106a-106c directly contacting dielectric wall 119-1 as shown in region 153 in the mirrored and annotated Chen FIG. 24A below) and the second end of the second set of nanosheets directly contacting the left sidewall of the second dielectric bar (semiconductor layers 106a-106c directly contacting dielectric wall 119-2 as shown in region 155 in the mirrored and annotated Chen FIG. 24A below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Hsu with the forksheet transistor structure of Chen to provide a transistor with greater device density and scalability (Chen [0036]).
Regarding dependent claim 20, Hsu, as modified by Chen, further discloses in Hsu FIG. 2G and 4 and associated text the first conductive layer is a gate metal of an n-type transistor, and the second conductive layer is a gate metal of a p-type transistor (gate 107c is part of an NMOS transistor and gate 107b is part of a PMOS transistor [0047] in Hsu FIG. 2G, corresponding to gates 108e and 108d respectively in the structure depicted in the figure above and Hsu FIG. 4); the second dielectric bar has a height higher than a height of the first dielectric bar (Hsu FIG. 4); and the second dielectric bar has a top surface that is coplanar with a top surface of a metal connection that connects the first conductive layer with the second conductive layer (a portion of the dielectric material between gates 108d and 108c extends up to the top surface of the metal layer 112a which connects gates 108d and 108c).
Additionally, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to design the semiconductor device as disclosed with a height of the second dielectric such that the second dielectric bar has a top surface that is coplanar with a top surface of the metal connection because Applicant has not disclosed that the height or coplanar relationship between the top surfaces of the second dielectric bar and metal connection provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with a taller dielectric bar or dielectric material with a top surface above the top surface on the metal connection because other elements of the claimed invention do not depend on these factors and Applicant’s specification and drawings depict additional dielectric material above the top surface of the second dielectric bar with no claimed material difference between these structures. The position and alignment of the top surface of the dielectric bar therefore appears to be arbitrary. Therefore, it would have been an obvious matter of design choice to provide a semiconductor device as disclosed where the second dielectric bar is designed and/or defined such that it has a top surface coplanar to that of the metal connection.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, and further in view of Chen and Koh et al. (US 20240088218 A1, hereinafter Koh).
Regarding dependent claim 19, Hsu, as modified by Chen, further discloses in Hsu FIG. 4 and associated text a metal connection on top of the first dielectric bar (gates 108d and 108e are connected through metal contacts 113 and metal layer 112a). They do not explicitly disclose the metal connection has a left sidewall that directly contacts the first conductive layer and has a right sidewall that directly contacts the second conductive layer.
However, in the same field of endeavor, Koh discloses in Koh FIG. 14B and associated text the metal connection has a left sidewall that directly contacts the first conductive layer and has a right sidewall that directly contacts the second conductive layer (the middle portion of conductive bridge 1302, as shown in the annotated figure below, is interpreted as the metal connection while the side portions of 1302 are interpreted as corresponding to upper portions of the first and second conductive layers since, as claimed, there is no material difference between the side portions of conductive bridge 1302 and upper portions of the first and second conductive layers or between the metal connection and first and second conductive layers. The position and alignment of the sidewalls of the metal connection therefore appears to be arbitrary.).
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Additionally, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to design the semiconductor device as disclosed such that the metal connection contacts the first and second conductive layers through either a bottom surface or sidewalls because Applicant has not disclosed that the metal connection has a left sidewall that directly contacts the first conductive layer and has a right sidewall that directly contacts the second conductive layer provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with the metal connection contacts the first and second conductive layers through a bottom surface because the bottom surface of conductive bridge 1302 is also capable of making electrical contact with the conductive layers. Additionally, as claimed, there is no material difference between the side portions of conductive bridge 1302 and upper portions of the first and second conductive layers or between the metal connection and first and second conductive layers. The position and alignment of the sidewalls of the metal connection therefore appears to be arbitrary. Therefore, it would have been an obvious matter of design choice to design and/or define the first and second conductive layers and metal connection such that the metal connection has a left sidewall that directly contacts the first conductive layer and has a right sidewall that directly contacts the second conductive layer.
Regarding dependent claim 20, While Hsu, as modified by Chen, is considered to disclose each and every distinct feature of claim 20 as set forth in the rejection above, the following additional grounds of rejection is made. Hsu, as modified by Chen, further discloses in Hsu FIG. 2G and 4 and associated text the first conductive layer is a gate metal of an n-type transistor, and the second conductive layer is a gate metal of a p-type transistor (gate 107c is part of an NMOS transistor and gate 107b is part of a PMOS transistor [0047] in Hsu FIG. 2G, corresponding to gates 108e and 108d respectively in the structure depicted in the figure above and Hsu FIG. 4) and a metal connection that connects the first conductive layer with the second conductive layer (a portion of the dielectric material between gates 108d and 108c extends up to the top surface of the metal layer 112a which connects gates 108d and 108c). They do not explicitly disclose the second dielectric bar has a height higher than a height of the first dielectric bar; and the second dielectric bar has a top surface that is coplanar with a top surface of the metal connection.
However, in the same field of endeavor, Koh discloses in Koh FIG. 14B and associated text the second dielectric bar has a height higher than a height of the first dielectric bar; and the second dielectric bar has a top surface that is coplanar with a top surface of the metal connection (as shown in annotated Koh FIG. 14B above).
Additionally, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to design the semiconductor device as disclosed with a height of the second dielectric such that the second dielectric bar has a top surface that is coplanar with a top surface of the metal connection because Applicant has not disclosed that the height or coplanar relationship between the top surfaces of the second dielectric bar and metal connection provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with a taller dielectric bar or dielectric material with a top surface above the top surface on the metal connection because other elements of the claimed invention do not depend on these factors and Applicant’s specification and drawings depict additional dielectric material above the top surface of the second dielectric bar with no claimed material difference between these structures. The position and alignment of the top surface of the dielectric bar therefore appears to be arbitrary. Therefore, it would have been an obvious matter of design choice to provide a semiconductor device as disclosed where the second dielectric bar is designed and/or defined such that it has a top surface coplanar to that of the metal connection.
Claims 3-4, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, and further in view of Chen and Kim et al. (US 20200373301 A1, hereinafter Kim).
Regarding dependent claim 3, Hsu, as modified by Chen, discloses the semiconductor structure of claim 2. They do not explicitly disclose a first source/drain (S/D) region next to a first side of the first set of nanosheets, and a first backside contact in conductive contact with a bottom surface of the first S/D region.
However, in the same field of endeavor, Kim discloses in Kim FIG. 1 and 5 and associated text a first source/drain (S/D) region next to a first side of the first set of nanosheets (source/drain pattern SD1 next to first channel regions CHP), and a first backside contact in conductive contact with a bottom surface of the first S/D region (upper contact UAC and upper via UV contact a surface of SD1, which will be considered the bottom surface, as shown in the figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hsu and Kim to integrate the gate and nanosheet structure of Hsu with the source/drain region and contact of Kim to form a transistor integrated in a semiconductor structure as disclosed by Kim.
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Regarding dependent claim 4, Hsu, as modified by Chen and Kim, further discloses in Kim FIG. 1 and 5 and associated text a second S/D region next to a first side of the second set of nanosheets (source/drain pattern SD2 is next to a side of channel region CH2, which would be comprised of the silicon layers 116 corresponding to gate 108d in Hsu FIG. 4 (second set of nanosheets) as combined), and a second backside contact in conductive contact with a bottom surface of the second S/D region (another upper contact UAC and upper via UV contacting a surface of SD2, which will be considered the bottom surface, as shown in FIG. 1). The cross-sectional view of FIG. 5 and the figure above show similar structures as those which would be shown in an offset cross-section intersecting SD2.
Regarding dependent claim 18, Hsu, as modified by Chen, discloses the semiconductor structure of claim 17. They do not explicitly disclose a first source/drain (S/D) region next to a first side of the first set of nanosheets, and a first backside contact in conductive contact with a bottom surface of the first S/D region.
However, in the same field of endeavor, Kim discloses in Kim FIG. 5 and associated text a first source/drain (S/D) region next to a first side of the first set of nanosheets (source/drain pattern SD1), and a first backside contact in conductive contact with a bottom surface of the first S/D region (upper contact UAC and upper via UV).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Hsu, as modified by Chen, and Kim to integrate the gate and nanosheet structure of Hsu with the source/drain region and contact of Kim to form a transistor integrated in a semiconductor structure as disclosed by Kim.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu, and further in view of Chen, Kim, and Koh.
Regarding dependent claim 5, Hsu, as modified by Chen and Kim, further discloses in Hsu FIG. 4 and associated text a metal connection on top of the first dielectric bar, the metal connection directly connects the first conductive layer with the second conductive layer (gates 108d and 108e are connected through metal contacts 113 and metal layer 112a as shown in the figure below). They do not explicitly disclose the metal connection has a left sidewall vertically aligned with the left sidewall of the first dielectric bar or a right sidewall vertically aligned with the right sidewall of the first dielectric bar.
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However, in the same field of endeavor, Koh discloses in Koh FIG. 14B and associated text the metal connection has a left sidewall vertically aligned with the left sidewall of the first dielectric bar and a right sidewall vertically aligned with the right sidewall of the first dielectric bar (the middle portion of conductive bridge 1302, as shown in the annotated figure below, is interpreted as the metal connection while the side portions of 1302 are interpreted as corresponding to upper portions of the first and second conductive layers since, as claimed, there is no material difference between the side portions of conductive bridge 1302 and upper portions of the first and second conductive layers or between the metal connection and first and second conductive layers. The position and alignment of the sidewalls of the metal connection therefore appears to be arbitrary.).
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Additionally, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to design the semiconductor device as disclosed such that the metal connection optionally spans the first and second conductive layers in addition to the first dielectric wall because Applicant has not disclosed that the metal connection having a left sidewall vertically aligned with the left sidewall of the first dielectric bar and a right sidewall vertically aligned with the right sidewall of the first dielectric bar provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with the metal connection optionally spans the first and second conductive layers in addition to the first dielectric wall because, as claimed, there is no material difference between the side portions of conductive bridge 1302 and upper portions of the first and second conductive layers or between the metal connection and first and second conductive layers. The position and alignment of the sidewalls of the metal connection therefore appears to be arbitrary. Therefore, it would have been an obvious matter of design choice to design and/or define the first and second conductive layers and metal connection such that the metal connection has a left sidewall vertically aligned with the left sidewall of the first dielectric bar and a right sidewall vertically aligned with the right sidewall of the first dielectric bar.
Regarding dependent claim 6, Hsu, as modified by Chen, Kim, and Koh, further discloses in Hsu FIG. 2G and 4 and Koh FIG. 14B and associated text the first conductive layer is a gate metal of an n-type transistor, and the second conductive layer is a gate metal of a p-type transistor (Hsu: gate 107c is part of an NMOS transistor and gate 107b is part of a PMOS transistor [0047] in Hsu FIG. 2G, corresponding to gates 108e and 108d respectively in the structure depicted in the figure above and Hsu FIG. 4); the second dielectric bar has a height higher than a height of the first dielectric bar; and the second dielectric bar has a top surface that is coplanar with a top surface of the metal connection (as shown in the annotated Koh FIG. 14B above).
Regarding dependent claim 7, Hsu, as modified by Chen, Kim, and Koh, further discloses in Hsu FIG. 4 and associated text a third dielectric bar (bar-shaped insulating material between gates 108e and 108f); a third set of nanosheets (silicon layers 116 corresponding to gate 108f); and a third conductive layer (gate 108f), wherein the third dielectric bar has a left sidewall and a right sidewall with the right sidewall of the third dielectric bar being parallel to the left sidewall of the first dielectric bar and wherein the first conductive layer separates the first set of nanosheets from the right sidewall of the third dielectric bar; the third set of nanosheets has a second end directly adjacent to the left sidewall of the third dielectric bar; and the third conductive layer is directly adjacent to the left sidewall of the third dielectric bar and surrounds the third set of nanosheets (structural limitations as claimed are shown in the figure below).
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Regarding dependent claim 8, Hsu, as modified by Chen, Kim, and Koh, further discloses in Hsu FIG. 2C and 5 and associated text a first mid-of-line (MOL) contact in conductive contact with a top surface of the first conductive layer (gate electrode GE (first conductive layer) contacts gate contact GC and lower via LV (first MOL contact) as shown in Kim FIG. 2C); a third S/D region next to a first side of the third set of nanosheets (another source/drain region in source/drain pattern SD1, corresponding to the portion of AP1 separate from that shown in Kim FIG. 5, is next to a side of channel region CH1, which would be comprised of the silicon layers 116 corresponding to gate 108f in Hsu FIG. 4 (third set of nanosheets) as combined); and a second MOL contact in conductive contact with a top surface of the third S/D region (lower contact LAC, as shown in the figure below). The cross-sectional view below is based on FIG. 5 but is intended to illustrate similar structures in an offset cross-section intersecting the portion of AP1 separate from that shown in Kim FIG. 5.
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Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu, and further in view of Chen, Kim, Koh, and Jung et al. (US 20230352408 A1, hereinafter Jung).
Regarding dependent claim 9, Hsu, as modified by Chen, Kim, and Koh, discloses in Kim FIG. 2C and 5 and associated text the semiconductor device of claim 8, further comprising a first backside power rail (BSPR) in contact with the first backside contact (upper interconnection lines POR1 and POR2 may be a power rail [0034]; POR1 (first BSPR) contacts first source/drain patterns SD2 through upper contact UAC and upper via UV (first backside contact), FIG. 5); a second BSPR in contact with the second backside contact (POR2 (second BSPR) contacts second source/drain patterns SD2 through upper contact UAC and upper via UV (second backside contact), [0034]); and a back-end-of-line (BEOL) in contact with the first and the second MOL contact (lower interconnection lines LML (BEOL) contact gate contact GC and lower contact LAC through lower vias LV (first and second MOL contacts), FIG. 2C and 5). The disclosures as combined do not explicitly disclose a backside power distribution network (BSPDN) in contact with the first and the second BSPRs.
However, in the same field of endeavor, Jung discloses in Jung FIG. 2A and associated text a backside power distribution network (BSPDN) in contact with the first and the second BSPRs (BSPDN 60 is in contact with multiple back-side power rails 54).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Hsu and Kim with the a BSPDN in contact with BSPRs as disclosed by Jung to provide power to the semiconductor device through BSPRs which may “simplify the… back-end-of-line (BEOL) portion of device fabrication so as to increase the integration density of the device” (Jung [0003]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 10192819 B1, pertaining to a semiconductor device with vertically stacked field effect transistors, a back-end-of-line, and middle of line.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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