DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/16/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 8, 10, 13-15, 17-19 and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US PG Pub 2019/0131390 to Huang et al (hereinafter Huang).
Regarding Claim 1, Huang discloses a field-effect transistor (FET), comprising:
a dielectric structure having a gate dielectric (13, Figs. 8A/8B) and a shielding dielectric (13’), the shielding dielectric being thicker than the gate dielectric and adjoining or being spaced apart from the gate dielectric along a first lateral direction (Fig. 8B);
a channel region of a first conductivity type (22, [0050]) adjoining a lower side of the gate dielectric; and
an auxiliary region (49, [0055]) of a second conductivity type adjoining the lower side of the gate dielectric and adjoining the channel region along a second lateral direction.
Regarding Claim 2, Huang discloses the FET of Claim 1, wherein the FET is a lateral depletion type FET.
Regarding Claim 3, Huang discloses the FET of Claim 1, wherein the channel region and the auxiliary region are arranged alternating along the second lateral direction (Fig. 8A).
Regarding Claim 4, Huang discloses the FET of Claim 1, wherein the auxiliary region is a part of a well region (24, [0050]) of the second conductivity type, which adjoins a lower side of a part of the channel region.
Regarding Claim 8, Huang discloses the FET of Claim 1, wherein the first channel region and the auxiliary region respectively extend in a form of a strip along the first lateral direction (Fig. 8A).
Regarding Claim 10, Huang discloses the FET of Claim 8, wherein a strip length of the channel region along the first lateral direction is greater than a strip length of the auxiliary region along the first lateral direction (Fig. 8A).
Regarding Claim 13, Huang. The FET of Claim 1, further comprising:
a drain extension region (14, Fig. 4B) of the first conductivity type adjoining a lower side of the shielding dielectric.
Regarding Claim 14, Huang discloses the FET of Claim 13, wherein a part of the drain extension region adjoins a lower side of a part of the channel region (Fig. 4B).
Regarding Claim 15, Huang discloses the FET of Claim 13, wherein the drain extension region is suitable for blocking a drain- to-source voltage in a range of from 5 V to 200 V [0044].
Regarding Claim 17, Huang discloses the FET of Claim 1, wherein the shielding dielectric is a shallow trench isolation structure or a LOCOS (local oxidation of silicon) structure (Fig. 8B).
Regarding Claim 18, Huang discloses the FET of Claim 1, wherein a thickness of the shielding dielectric exceeds a thickness of the gate dielectric by from 100% to 600% (Fig. 8B).
Regarding Claim 19, Huang discloses an integrated circuit comprising the FET of Claim 1 [0081].
Regarding Claim 21, Huang discloses the integrated circuit of Claim 19, wherein the FET is interconnected as a high-side switch to provide a supply voltage for a logic circuit unit [0080].
Regarding Claim 22, Huang discloses a method for forming a field-effect transistor (FET), the method comprising:
forming a dielectric structure having a gate dielectric (13, Fig. 8B) and a shielding dielectric (13’), the shielding dielectric being thicker than the gate dielectric and adjoining or being spaced apart from the gate dielectric along a first lateral direction (Fig. 8B);
forming a channel region (22, [0050]) of a first conductivity type, which adjoins a lower side of the gate dielectric; and
forming an auxiliary region (49, [0055]) of a second conductivity type, which adjoins the lower side of the gate dielectric and adjoins the channel region along a second lateral direction.
Regarding Claim 23, Huang discloses the method of Claim 22, further comprising:
forming a drain extension region (14, Fig. 4B) of the first conductivity type, which adjoins a lower side of the shielding dielectric.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang.
Regarding Claims 5 and 6, Huang discloses the FET of Claim 4 but does not explicitly disclose the dopant profile.
However, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to have formed the doped regions such that “the well region has a first vertical profile of dopants of the second conductivity type, and a maximum dopant concentration of the first vertical profile lies in a range of from 10.sup.17 cm.sup.-3 to 5x10.sup.17 cm.sup.-3; and wherein the channel region has a second vertical profile of dopants of the first conductivity type, and a maximum dopant concentration of the second vertical profile lies in a range of from 10.sup.17 cm.sup.-3 to 3x10.sup.18 cm.sup.-3”.
Absent any unexpected results by Applicant, it would have been obvious to have doped the regions to the levels claimed by Applicant since they were within ranges normally found in the art for semiconductor well regions. Huang notes that the well region and channel region are doped such that a super junction can be generated by the depletion effect [0041]-[0044]. The large range of dopant concentration claimed by Applicant for the two regions include doping amounts which would function within the operation of Huang’s device.
Regarding Claim 7, Huang makes obvious the FET of Claim 6, wherein the dopants of the first vertical profile in the channel region partially compensate for the dopants of the second vertical profile in the channel region [0042].
Allowable Subject Matter
Claims 9, 11, 12, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 requires the strip width of the channel region along the second lateral direction range from two to twenty times as great as a strip width of the auxiliary region along the second lateral direction. Huang does not disclose such an embodiment. Claims 11, 12, 16 and 20 require the channel region, auxiliary region and/or a deep body region be electrically connected in different manners that are not disclosed or suggested in Huang.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID C SPALLA whose telephone number is (303)297-4298. The examiner can normally be reached Mon-Fri 10am-5pm MST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DAVID C SPALLA/ Primary Examiner, Art Unit 2893