Prosecution Insights
Last updated: May 29, 2026
Application No. 18/487,430

INTEGRATED CIRCUIT AND IMAGE SENSOR INCLUDING THE SAME

Non-Final OA §102§103
Filed
Oct 16, 2023
Priority
Feb 21, 2023 — RE 10-2023-0023153
Examiner
GHYKA, ALEXANDER G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1078 granted / 1289 resolved
+15.6% vs TC avg
Moderate +14% lift
Without
With
+13.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
30 currently pending
Career history
1320
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
70.9%
+30.9% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
5.7%
-34.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1289 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species A (Claims 1-11) in the reply filed on 1/13/2026 is acknowledged. The traversal is on the ground(s) that the search and examination of all the claims in an application may be made without serious burden. This is not found persuasive because the species contain mutually exclusive claim elements, and are classified in different classes, which would constitute a serious burden. Rejoinder issues will be addressed upon indication of allowable subject matter. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 and 5-9 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Kang et al (US 2021/0358902) . The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. With respect to Claim 1, Kang et al discloses an integrated circuit (Figures 1-3B) comprising; at least one cell (Figure 2, LTC, paragraph 31); a planar transistor (paragraph 31); and a vertical transistor (paragraph 31); wherein the at least one cell comprises a first active region (RX1, paragraph 32-33) and a second active region (RX2, paragraphs 32-33) adjacent to each other; at least one first active fin (F1. Paragraphs 33-34) ) on the first active region and extending in a first direction (Figure 2, horizontal); at least one second active fin (F2, paragraphs 33-34) on the second active region and extending in the first direction (Figure 2, horizontal); and an active gate line (Figures 2 and 3B, GL) vertically overlapping the first active region and the second active region and extending in a second direction perpendicular (Figure 2, vertical) to the first direction. See Figures 1-3B and corresponding text, especially paragraphs 21-34. With respect to Claim 2, Kang et al discloses the at least one cell is defined by a cell boundary having a width in the first direction and a height in the second direction. See Figure 1 and corresponding text. With respect to Claim 3, Kang et al discloses an active gate line (GL) intersects with the at least one first active fin (F1) on the first active region (RX1), and each of the first active region and the second active region is independently an NMOS transistor or a PMOS transistor region (paragraph 37). See Figures 2 and 3B, and corresponding text). With respect to Claim 5, Kang et al disclose wherein the common voltage is configured to be connected to at least one of a drain voltage VDD or ground. See paragraph 24. With respect to Claim 6, Kang et al discloses a first contact on a portion of the active gate line; and second contacts on the at least one first active fin and on both sides of the active gate line. See paragraphs 41 and 52-56. With respect to Claim 7, Kang et al discloses wherein the at least one first active fin (F1) and the at least one second active fin (F2) are spaced apart from each other at regular intervals. See Figure 2 of Kang et al. With respect to Claim 8, Kang et al discloses further comprising a spacer film (paragraph 24) between the at least one first active fin and the at least one second active fin. See paragraph 24 of Kang et al. With respect to Claim 9, Kang et al disclose wherein neither the first active region nor the second active region include a dummy gate line. See Figures 1-3B of Kang et al. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 4 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al (US 2021/0358902). With respect to Claim 4, Kang et al is relied upon as discussed above. Moreover, Kang et al disclose multiple cells (paragraph 2), a common voltage(paragraphs 95-96) and power rails (PR) connecting the cells (Figure 1). However, Kang et al does not explicitly disclose wherein mutually adjacent cell arrays share a node configured for application of a common voltage thereto. The Examiner takes Official Notice that it is well known in the art to form cell array cells for multiple cells, which are electrically connected through nodes, to apply a voltage. It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to form mutually adjacent cell arrays to share a node configured for application of a common voltage thereto, for its well known benefit in the art of applying a voltage to all the cells. With respect to Claims 10-11, Kang et al is relied upon as discussed above. Moreover, Kang et al disclose connection metals ( C ) between fins, wiring in and out (Figures 1-3B), source/ drain regions and via (paragraphs 50-54, and connection wiring (paragraphs 43-44). Kang et al does not explicitly disclose the input and output wiring, the connection vias and connection wiring and their relative direction. With respect to Claims 10-11, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to arrive at the presently claimed wiring, as the specific components and their direction would have been within the skill of one of ordinary skill in the art, as rearrangement of parts. See In re Japikse, 86 USPQ 70 (CCPA 1950). The placement of known electrical connections for their known benefit would have been within the skill of one of ordinary skill in the art. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. AGG March 17, 2026 /ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Oct 16, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §102, §103
May 01, 2026
Interview Requested
May 11, 2026
Examiner Interview Summary
May 11, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
97%
With Interview (+13.8%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1289 resolved cases by this examiner. Grant probability derived from career allowance rate.

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