Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/16/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. US 2015/0221663 in view of ABE US 2019/0244968 and Shen et al. US 2014/0073126.
Re claim 1, Tan teaches a method of manufacturing a single poly non-volatile memory device (fig2a), the method comprising:
forming an insulated isolation region (280, fig9a, [42]) in a substrate (201, fig9a, [30]);
forming a first well region (207, fig9b, [32, 38]) and a second well region (250, fig9b, [36, 37]) in the substrate;
Tan does not explicitly show forming a mask pattern exposing a first portion of the first well region, and covering a second portion of the first well region and the second well region; performing a nitrogen ion implantation process on the substrate with the mask pattern to form a nitrogen region in the first portion of the first well region.
ABE teaches forming a mask pattern (PR1, fig7, [80]) exposing a first portion (1Aa, fig7, [91]) of the first well region (PW, fig7, [91]), and covering a second portion (1Ab, fig7, [64]) of the first well region and the second well region (NW1, NW2, fig7); performing a nitrogen ion implantation process (form NL, fig7, [91]) on the substrate with the mask pattern to form a nitrogen region (NL, fig7, [91]) in the first portion of the first well region.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tan and ABE to add nitrogen-introduction portion in channel region for storage transistor 130. The motivation to do so is to improve retention property of the transistor (ABE, [163]) by reducing leakage current (ABE, [163]).
Tan teaches performing an oxidation process (thermal oxidation 926, fig9c, [110]) on the first portion of the first well region, the second portion of the well region, and the second well region to simultaneously form a sensing gate insulating film (226 of 130, fig9d, [44]), a selection gate insulating film (226 of 110, fig9d, [44]), and a control gate insulating film (226 of 150 in region BB’, fig9d, [44]), respectively; and
forming a sensing gate (228 of 130, fig9d, [44]), a selection gate (228 of 110, fig9d, [44]), and a control gate (228 of 150 in region BB’, fig9d, [44]) on the sensing gate insulating film, the selection gate insulating film, and the control gate insulating film, respectively,
Tan does not explicitly show wherein a thickness of the sensing gate insulating film is smaller than a thickness of the selection gate insulating film and a thickness of the control gate insulating film.
Shen teaches a thickness of the sensing gate insulating film (112, fig1E, [36]) is smaller than a thickness of the selection gate insulating film (116, fig1E, [38]) and a thickness of the control gate insulating film (114, fig1E, [37]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tan and Shen to adjust the thickness of the sensing gate insulating film thickness to be smaller than the selection gate insulating film and the control gate insulating film. The motivation to do so is to have a low operating voltage and high driving capability and high information guidance speed (Shen, [28, 29]).
Re claim 2, Tan modified above teaches the method of claim 1, further comprising forming a source region (214/234, fig2b, [46]) and a drain region (232, fig2b, [46]) adjacent to the sensing gate insulating film (226 of 130, fig9d, [44]), wherein the nitrogen region (NL added between 234 and 232 for transistor 130, fig2b) is disposed between the source region and the drain region, and disposed under the sensing gate insulating film (226 of 130, fig2b ).
Re claim 3, Tan modified above teaches the method of claim 1, wherein the nitrogen region (NL added under 226 between 234 and 232 for transistor 130, fig2b) is disposed closer to the sensing gate insulating film than the selection gate insulating film.
Re claim 4, Tan modified above teaches the method of claim 1, wherein a thickness of the control gate insulating film (226 of 150 in region BB’, fig2b and 9d, [44]) is equal to a thickness of the selection gate insulating film (226 of 110, fig2b and 9d, [44]).
Re claim 5, Tan modified above teaches the method of claim 1, wherein the sensing gate (228 of 130, fig2a and 2b, [44]) and the control gate (228 of 150 in region BB’, fig2a and 2b, [44]) are physically and electrically connected.
Claim(s) 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. US 2015/0221663 in view of ABE US 2019/0244968.
Re claim 13, Tan teaches a method of manufacturing a single poly non-volatile memory device (fig2a), the method comprising:
forming an insulated isolation region (280, fig9a, [42]) in a substrate (201, fig9a, [30]);
forming a first well region (207, fig9b, [32, 38]) and a second well region (250, fig9b, [36, 37]) in the substrate;
Tan does not explicitly show performing a nitrogen ion implantation process on the first and second well regions to form a first nitrogen region and a second nitrogen region in the first and second well regions, respectively;
ABE teaches performing a nitrogen ion implantation process (fig31, [150]) on the first (PW, fig31, [91]) and second well regions (NW1, NW2, fig31) to form a first nitrogen region (NL in 1A, fig31) and a second nitrogen region (NL in 2A or 3A, fig31) in the first and second well regions, respectively;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tan and ABE to add nitrogen-introduction portion in channel region. The motivation to do so is to improve retention property of the transistor (ABE, [163]) by reducing leakage current (ABE, [163]).
Tan teaches performing an oxidation process (thermal oxidation 926, fig9c, [110]) on the first well region and the second well region to simultaneously form a sensing gate insulating film (226 of 130, fig9d, [44]) and a control gate insulating film (226 of 150 in region BB’, fig9d, [44]), respectively; and
forming a sensing gate (228 of 130, fig9d, [44]) and a control gate (228 of 150 in region BB’, fig9d, [44]) on the sensing gate insulating film and the control gate insulating film, respectively,
wherein the sensing gate insulating film (226 of 130, fig9d, [44]) has a same thickness as the control gate insulating film (226 of 150 in region BB’, fig9d, [44]), and
wherein the sensing gate and the control gate are electrically connected (fig2a).
Re claim 14, Tan modified above teaches the method of claim 13, wherein the first nitrogen region and the second nitrogen region are formed under the sensing gate insulating film and the control gate insulating film (Tan, NL added under 226, fig2b), respectively.
Re claim 15, Tan modified above teaches the method of claim 13, further comprising: performing a control gate ion implantation process (Tan, 210, fig9b, [109]) on the substrate to form a control gate ion implantation region (Tan, 210 in BB’, fig9b, [109]) in the second well region (Tan, 250, fig9b, [109]), wherein the control gate ion implantation region (Tan, 210, fig9b, [109]) is formed under the control gate insulating film (Tan, 226 in BB’, fig9d), and overlaps the second nitrogen region (Tan, NL added between 226 and 250, fig9d).
Allowable Subject Matter
Claims 7-12 are allowed.
Claim 6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
The following is an examiner’s statement of reasons for allowance: currently independent claim 7 is allowable because the closest prior art does not appear to disclose, alone or in combination, the limitations of “forming a mask pattern exposing a first portion of the first well region and the second well region, and covering a second portion of the first well region; performing a nitrogen ion implantation process on the substrate with the mask pattern to form a first nitrogen region in the first portion of the first well region, and form a second nitrogen region in the second well region” in combination with the other required elements of the claim 7.
Specifically, the limitations are material to the inventive concept of the application in hand to prevent leakage current from flowing in over erase state, improves efficiency of write and erase operation, and reduces area of the device.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812