DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed April 16, 2026, in which: claims 1, 4-5, and 7 are amended; claims 2-3 are cancelled; and the rejection of the claims are traversed. Claims 1 and 4-10 are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant’s arguments, see page 5-7, filed April 16, 2026, with respect to the rejection(s) of claim(s) 1 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sasaki et al. (US 10263015 B2, hereinafter Sasaki) which discloses the limitation “the via hole shares a sidewall with the opening” added to claim 1 by Applicant’s amendment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Regarding independent claim 1, Sasaki discloses in Sasaki FIG. 235-246 and associated text A method for manufacturing a vertical channel thin film transistor, the method comprising: forming a bottom source drain electrode (lower electrode 120Z); forming a first interlayer insulating layer on the bottom source drain electrode (insulating layer 130Z); forming a first middle source drain electrode on the first interlayer insulating layer (upper electrode 140Z); forming a second interlayer insulating layer on the first middle source drain electrodes (insulating layer 150Z); removing portions of the second interlayer insulating layer and the first interlayer insulating layer to form an opening through which portions of the bottom source drain electrode and the first middle source drain electrodes are exposed (openings 135Z and 137Z collectively exhibit the structure of the claimed opening in that they expose insulating layers 130Z and 150Z and lower (bottom) and upper (first middle) electrodes 120Z and 140Z); forming a channel layer on sidewalls of the bottom source drain electrode, the first interlayer insulating layer, the first middle source drain electrodes, and the second interlayer insulating layer (oxide semiconductor layer 160Z is a channel layer); forming a gate insulating layer on the channel layers, the bottom source drain electrode, and the first middle source drain electrodes (gate insulating layer 170Z is formed on the entirety of the substrate shown in FIG. 244 (Sasaki (738))); removing a portion of the gate insulating layer to form a via hole through which one of the first middle source drain electrodes is exposed (gate insulating layer 170Z is etched, exposing upper electrode 140Z through opening 137Z, which is considered the via hole); and forming a gate electrode on the gate insulating layer (gate electrode 180Z), wherein the via hole shares a sidewall with the opening (opening 137Z shares a sidewall of the opening comprising openings 135Z and 137Z, specifically the exposed sidewalls of layers 110Z, 122Z, 130Z, 140Z, and 150Z). Sasaki does not explicitly disclose the first middle source drain electrode, the channel layer, and the gate electrode respectively comprise first middle source drain electrodes, channel layers, and gate electrodes (plural); forming a top source drain electrode on the second interlayer insulating layer; portions of the top source drain electrode are exposed through the opening; forming the channel layers on sidewalls of the top source drain electrode; or forming the gate insulating layer on the top source drain electrode.
However, in the same field of endeavor, Shen discloses in Shen FIG. 8 and associated text the first middle source drain electrode, the channel layer, and the gate electrode respectively comprise first middle source drain electrodes (electrodes 203 and 701 corresponding to Sasaki’s electrode 140Z), channel layers (active patterns 204 and 704 corresponding to Sasaki’s channel 160Z), and gate electrodes (gate electrodes 206 and 706 corresponding to Sasaki’s gate electrode 180Z); forming a top source drain electrode on the second interlayer insulating layer (703, which, in FIG. 8, labels the second middle source drain electrodes, also refers to a top source drain electrode, which is on insulating layer 702 corresponding to the claimed second interlayer insulating layer and Sasaki’s insulating layer 150Z; please refer to the annotated figure below); portions of the top source drain electrode are exposed through the opening; forming the channel layers on sidewalls of the top source drain electrode (active patterns 204/704 corresponding to the claimed channel layers and Sasaki’s insulating layer 160Z); and forming the gate insulating layer on the top source drain electrode (insulating layers 205/705 are gate insulating layers).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the thin film transistor of Sasaki with the top layer and multiples of first middle source drain electrode, channel layers, and gate electrodes of Shen to provide a die with additional individually controllable transistors by including multiple of the aforementioned structure and greater degree of integration by the inclusion of Shen’s third (top) or more source drain electrode. As combined, portions of the top source drain electrode are exposed through the opening in the same way portions of the bottom and first upper middle electrodes are exposed in Sasaki to connect to data lines.
Regarding dependent claim 4, Sasaki, as modified by Shen, further discloses in Sasaki FIG. 246 and 236 and associated text The method of claim 1, wherein the gate electrodes are connected to one of the first middle source drain electrodes by a via electrode within the opening (A conductive layer for the gate electrode 180Z, a source line 190Z and a drain line 192Z is formed on the entirety of the substrate (Sasaki (739)); at this stage the portion of the conductive layer in the via 137Z is considered the via electrode within the opening 137Z connecting to first middle source drain electrode 140Z and gate electrodes 180Z, thus exhibiting the claimed structure).
Regarding dependent claim 5, Sasaki, as modified by Shen, further discloses the method of claim 1, wherein the forming the gate electrodes comprises forming a via electrode in the via hole (A conductive layer for the gate electrode 180Z, a source line 190Z and a drain line 192Z is formed on the entirety of the substrate (Sasaki (739)); portions of the conductive layer described in via hole 137Z are the via electrode and formed in the same step as forming the gate electrode 180Z).
Regarding dependent claim 6, Sasaki, as modified by Shen, further discloses in Shen FIG. 8 and associated text forming second middle source drain electrodes on the second interlayer insulating layer (703); and forming a third interlayer insulating layer on the second middle source drain electrodes (702). Please refer to the following figure:
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Regarding dependent claim 7, Sasaki, as modified by Shen, further discloses in Shen FIG. 4 and associated text The method of claim 6, wherein the opening is formed between the second middle source drain electrodes (annular groove 100b is analogous to the opening of Sasaki as interpreted above and as claimed in that it exposes bottom and first middle source drain electrodes an is between transistors 20a and their respective first middle source drain electrodes. Although annular groove 100b is not shown in those of Shen’s drawings depicting the second middle source drain electrodes, the combined reference would exhibit the claimed structure since openings are provided for each of the source drain electrode layers to connect to data lines as disclosed by Sasaki and the openings would be formed between second middle source drain electrodes to separate adjacent thin film transistor groups 20b).
Regarding dependent claim 8, Sasaki, as modified by Shen, further discloses in Sasaki FIG. 2 and 50 and associated text The method of claim 1, wherein each of the first interlayer insulating layer and the second interlayer insulating layer comprises silicon oxide formed through a plasma enhanced chemical vapor deposition method (insulating layers 130 and 150E, corresponding to insulating layers 130Z and 150Z, are silicon oxide and formed by the same method as insulating layer 110 (Sasaki (344) and (445)), which may be formed by plasma CVD (Sasaki (340))).
Regarding dependent claim 9, Sasaki, as modified by Shen, further discloses in Sasaki FIG. 2 and 50 and associated text The method of claim 1, wherein the gate insulating layer comprises silicon oxide or metal oxide formed through a rapid heat treatment method or a chemical vapor deposition method (gate insulating layer 170, corresponding to gate insulating layer 170Z formed by the same material and method, may be silicon oxide or aluminum oxide and formed by the same method as layer 110, which may be formed by CVD (Sasaki (347) and (340))).
Regarding dependent claim 10, Sasaki, as modified by Shen, further discloses in Shen The method of claim 1, wherein each of the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode comprises molybdenum ([0044], bottom source/drain electrode 201 is molybdenum; [0050], first middle source/drain electrodes 203 are molybdenum; [0092], first middle source/drain electrodes 701 are the same material as 201; [0093] second middle source/drain electrodes 703, and top source/drain electrode 703 are the same material as 203).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20210210528 A1, a method of manufacturing thin film transistors with vertical channels.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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