DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the second middle source drain electrodes" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, Examiner will interpret this claim as “the first middle source drain electrodes”. Examiner recommends amending accordingly or amending to make claim 7 a dependent claim of claim 6.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 6-7, and 10 are rejected under 35 U.S.C. 102 (a)(2) as being anticipated by Shen et al. (US 20240014216 A1, hereinafter Shen).
Regarding independent claim 1, Shen discloses in FIG. 8 and associated text a method for manufacturing a vertical channel thin film transistor, the method comprising: forming a bottom source drain electrode (201); forming a first interlayer insulating layer on the bottom source drain electrode (202); forming first middle source drain electrodes on the first interlayer insulating layer (203 and 701); forming a second interlayer insulating layer on the first middle source drain electrodes (702); forming a top source drain electrode on the second interlayer insulating layer (703, which, in FIG. 8, labels the second middle source drain electrodes, also refers to a top source drain electrode); removing portions of the second interlayer insulating layer and the first interlayer insulating layer to form an opening through which portions of the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode are exposed ([0103], openings 100a3 and 100a4 expose the aforementioned features; [0069], openings 100a3 and 100a4 are formed by removal of first and second interlayer insulating layers 202 and 702); forming channel layers on sidewalls of the bottom source drain electrode, the first interlayer insulating layer, the first middle source drain electrodes, the second interlayer insulating layer, and the top source drain electrode (channel layers 204 and 704); forming a gate insulating layer on the channel layers, the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode (gate insulating layers 205 and 705); and forming gate electrodes on the gate insulating layer (gate electrodes 206 and 706). Please refer to the following figure:
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Regarding dependent claim 6, Shen further discloses in FIG. 8 and associated text forming second middle source drain electrodes on the second interlayer insulating layer (703); and forming a third interlayer insulating layer on the second middle source drain electrodes (702). Please refer to the following figure:
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Regarding dependent claim 7, Shen further discloses in FIG. 8 and associated text the opening is formed between the second middle source drain electrodes (as seen in the figure above).
Regarding dependent claim 10, Shen further discloses each of the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode comprises molybdenum ([0044], bottom source/drain electrode 201 is molybdenum; [0050], first middle source/drain electrodes 203 are molybdenum; [0092], first middle source/drain electrodes 701 are the same material as 201; [0093] second middle source/drain electrodes 703, and top source/drain electrode 703 are the same material as 203).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Shen, and further in view of Yamazaki et al. (US 20110101355 A1, hereinafter Yamazaki).
Regarding dependent claim 2, Shen discloses the method of claim 1. Shen does not explicitly disclose the further limitations of claim 2. However, in the same field of endeavor, Yamazaki in FIG. 7D and associated text discloses removing a portion of the gate insulating layer (117) to form a via hole (123) through which one of the first middle source drain electrodes is exposed (109). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shen and Yamazaki to provide a thin film transistor with via hole to attach a wire or further features to the exposed middle electrode, expanding the versatility of the transistor.
Regarding dependent claim 3, Shen, as modified by Yamazaki, does not explicitly disclose the via hole is formed on a sidewall of the opening. However, before the effective filing date of the invention, it would have been an obvious matter of design choice to a person of ordinary skill in the art to form a via on the sidewall of a vertical channel thin film transistor because Applicant has not disclosed that forming the via hole on the sidewall provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected Applicant’s invention to perform equally well with a via hole formed at the top of the thin film transistor as disclosed by Shen, as modified by Yamazaki because the position of the via hole is irrelevant to the efficacy of its primary function, being to allow for connection between a middle electrode and any further features of the thin film transistor. Therefore, it would have been an obvious matter of design choice to form the via hole on a sidewall of the opening.
Regarding dependent claim 4, Shen, as modified by Yamazaki, further discloses in Yamazaki FIG. 2B and associated text the gate electrodes (131 upper horizontal regions) are connected to one of the first middle source drain electrodes (109) by a via electrode within the opening (131 vertical regions within via hole 123). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shen and Yamazaki to provide a vertical channel thin film transistor stack in which a middle source/drain electrode can be configured to connect to an external device, improving the versatility of the transistor. Please refer to the following figure:
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Regarding dependent claim 5, Shen, as modified by Yamazaki, further discloses in Yamazaki FIG. 7D-7E and associated text the forming the gate electrodes comprises forming a via electrode in the via hole (as seen in Yamazaki FIG. 7D-7E, which depicts the thin film transistor before and after the step of forming the gate electrode and via electrode as identified in the figure above).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shen, and further in view of Ji et al. (KR 20210033878 A, hereinafter Ji)
Regarding dependent claim 8, Shen discloses the method of claim 1, wherein each of the first interlayer insulating layer and the second interlayer insulating layer comprises silicon oxide (Shen [0055], interlayer insulating layer 205 includes silicon oxide; Shen [0100], interlayer insulating layer 705 is made of the same material as insulating layer 205). Shen does not explicitly disclose the interlayer insulating layer is formed through a plasma enhanced chemical deposition method.
However, in the same field of endeavor, Ji discloses an interlayer insulating layer of silicon oxide formed through a plasma enhanced chemical vapor deposition method (Ji [0059]-[0060], interlayer insulating layer 120 is silicon oxide and formed through PECVD).
Ji’s known technique, as cited above, would have been recognized by one skilled in the art as applicable to the base thin film transistor of Shen and the results would have been predictable and resulted in greater uniformity of the insulating layer which results in an improved thin film transistor.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time of the effective filing date of the invention.
The rationale to support a conclusion that the claim would have been obvious is that a particular known technique was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shen, and further in view of Yoon et al. (KR 20110021632 A, hereinafter Yoon).
Regarding dependent claim 9, Shen discloses the method of claim 1. does not explicitly disclose the further limitations of claim 9. However, in the same field of endeavor, Yoon discloses the gate insulating layer comprises silicon oxide or metal oxide formed through a rapid heat treatment method or a chemical vapor deposition method (Yoon [0104], gate insulating layer 209 is formed by CVD; Yoon [0140], gate insulating layer 209 is aluminum oxide). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shen and Yoon to provide a thin film transistor with an insulating layer with high dielectric constant such as that of aluminum oxide to minimize leakage current and to form the layer using chemical vapor deposition for a high degree of conformity over three-dimensional topographies such as the claimed invention, improving the quality of the thin film transistor.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20210210528 A1, a method of manufacturing thin film transistors with vertical channels; and
US 20220005936 A1, a vertical transport field effect transistor which, despite not being a thin film transistor, shares several structural elements with the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Fri 7:30 a.m. - 5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897