DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 5/27/2026, in which: claim(s) 1, 6, 10, and 19 is/are amended; claim(s) 5 and 17 is/are cancelled; and the rejection of the claims are traversed. Claim(s) 1-4, 6-16, and 18-22 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed 5/27/2026, with respect to the rejection(s) of claim(s) 1, 7-9, and 19-20 have been fully considered but they are not persuasive. The broadest reasonable interpretation of “in contact with”, as used throughout the amended claims 1 and 19, does not preclude the existence of intervening layers. Therefore, the features relied upon in the previous rejection of limitations where one or more elements are “on” one or more other elements continue to read on said limitations, as amended, where the relationship has been amended to “in contact with” or similar language. A full rejection of the claims as amended follows.
Applicant’s arguments with respect to the rejection(s) of claim(s) 6, 10-11, 15, and 18-20 under 35 U.S.C. 102(a)(1) and/or 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chuang et al. (US 20200411751 A1, hereinafter Chuang). Chuang discloses a low-k material disposed between word lines to prevent crosstalk and parasitic capacitance, which would be obvious to combine with Kim and/or Chen.
Claim Objections
Claim 22 is objected to because of the following informalities: “…the low-k material filling in the space…” appears to be a typo, which should be corrected to “…the low-k material fills in the space…”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation "…the space defined by…". There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, Examiner interprets the claim as reciting “…[[the]] a space defined by”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 10, 11, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20120299090 A1, hereinafter Kim), and further in view of Chuang et al. (US 20200411751 A1, hereinafter Chuang).
Regarding independent claim 10, Kim discloses in Kim FIG. 88 and 95 and associated text a semiconductor device, comprising: a plurality of gate structures (please refer to the following figure); a channel layer between a first one of the plurality of gate structures and a second one of the plurality of gate structures (vertical channels VC); and a bit line in contact with the channel layer (BL), wherein each of the plurality of gate structures comprises: a first word line and a second word line that are spaced apart from each other (wordlines WL); a first gate dielectric layer on a first sidewall of the first word line (first and second gate insulators 32 and 42 are on a sidewall of each wordline WL); a second gate dielectric layer on a first sidewall of the second word line (first and second gate insulators 32 and 42 are on a sidewall of each wordline WL); and a gate capping layer in contact with a top surface of the first word line, a top surface of the second word line, a top surface of the first gate dielectric layer, and a top surface of the second gate dielectric layer (interlayer dielectric layer 73 caps the gate structures and is in either direct or indirect contact with all aforementioned features).
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Kim does not explicitly disclose a low-k material layer including a first sidewall and a second sidewall, the first sidewall of the low-k material layer in contact with a second sidewall of the first word line and the second sidewall of the low-k material layer in contact with a second sidewall of the second word line or the gate capping layer is in contact with a top surface of the low-k material layer.
However, in the same field of endeavor, Chuang discloses in Chuang Fig. 1 and associated text a low-k material layer (dielectric material 102 is low-k (Chuang [0027])) including a first sidewall and a second sidewall, the first sidewall of the low-k material layer in contact with a second sidewall of the first word line and the second sidewall of the low-k material layer in contact with a second sidewall of the second word line (102 is in contact with sidewalls of metal line(s) 108, which may be wordlines (Chuang [0027]); while only one is depicted, a large number of wordlines 108 may be in low-k layer 102, which would include second sidewalls of a first and second wordline in contact with first and second sidewalls of 102 as depicted in the annotated Chuang Fig. 1 below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the low-k material layer of Chuang with the semiconductor device of Kim, e.g. by replacing Kim’s FOX2 with the low-k material of Chuang’s 102, such that the gate capping layer is in contact with a top surface of the low-k material layer (73 is in contact with a top surface of FOX2, corresponding to the low-k material layer as combined) to reduce crosstalk and parasitic capacitance between wordlines (Chuang [0021], [0027]).
Regarding dependent claim 11, Kim, as modified by Chuang, further discloses in Kim FIG. 95 and associated text the top surface of the first word line, the top surface of the second word line, the top surface of the first gate dielectric layer, and the top surface of the second gate dielectric layer are coplanar with each other (top surfaces of the aforementioned features are coplanar as depicted).
Regarding dependent claim 18, Kim, as modified by Chuang, discloses the semiconductor device of claim 10, but does not explicitly disclose the top surface of the first word line, the top surface of the second word line, the top surface of the first gate dielectric layer, and the top surface of the second gate dielectric layer are at respective heights that are lower than a height of a top surface of the channel layer with respect to the bit line.
However, Kim discloses in Kim FIG. 3B and associated text a height of a top surface of the channel layer with respect to the bit line is higher than a bottom surface of part of the word lines (A bottom surface of the second impurity-implanted region 20 (corresponding to a top surface of the vertical chancel C/VC) may be higher than a bottom surface of the second sub-gate pattern SG2 (corresponding to a point somewhere between the top and bottom surfaces of the word lines), (Kim [0095])). Moreover, Kim recognizes the length of a channel (or height, in the case of vertical channels) as a result effective variable (a channel length may relatively increase to improve subthreshold characteristics and/or a threshold voltage distribution, (Kim [0101])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vertical channels of Kim to be greater than the heights of the word lines and gate dielectric layers. One would have chosen the height of the channel according to a result effective variable to provide a transistor with threshold voltage or other characteristics suited to the application of the transistor. One would have been motivated to form the channel to have a height within the claimed range to improve threshold characteristics of the transistor.
Claims 1, 7-9, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, and further in view of Chen et al. (US 20210408267 A1, hereinafter Chen).
Regarding independent claim 1, Kim discloses in Kim FIG. 88 and 95 and associated text a semiconductor device, comprising: a bit line (BL); a first word line and a second word line (wordlines WL; please refer to the following figure); a first gate dielectric layer in contact with a first sidewall of the first word line (first and second gate insulators 32 and 42 are in contact with sidewalls of each wordline WL); a second gate dielectric layer in contact with a first sidewall of the second word line (first and second gate insulators 32 and 42 are in contact with sidewalls of each wordline WL); channel layers that are spaced apart from one another (vertical channels VC, spaced apart as depicted), wherein the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer are between a first one of the channel layers and a second one of the channel layers (each aforementioned feature is between vertical channels VC as depicted).
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Kim does not explicitly disclose a support dielectric layer in contact with a top surface of the bit line, the first word line and the second word line in contact with a top surface of the support dielectric layer, or the support dielectric layer is between the first and second channel layers.
However, in the same field of endeavor, Chen discloses in Chen FIG. 20 and associated text a support dielectric layer in contact with a top surface of the bit line (bottom spacer layer 149 is a dielectric (Chen [0078]) in (indirect) contact with a top surface of source/drain structures 143 (corresponding to contact regions of a bit line)), the first word line and the second word line in contact with a top surface of the support dielectric layer (gate electrode layers 153a2 and 153b2 (corresponding to the first and second word lines claimed and their counterparts in Kim) are in (indirect) contact with a top surface of bottom spacer 149), and the support dielectric layer is between the first and second channel layers (bottom spacer 149 is between semiconductor fins 123a and 123b (corresponding to the first and second channel layers claimed and their counterparts in Kim)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim with the bottom spacer layer and corresponding structure of Chen to provide a transistor with gates isolated by the bottom spacer to cover and isolate underlying structures from the gate contacts.
Regarding dependent claim 7, Kim, as previously modified by Chen, discloses the semiconductor device of claim 1. However, as previously modified, the combination does not explicitly disclose each of the channel layers comprises: a lower channel portion in contact with the bit line; and a plurality of upper channel portions on the lower channel portion, wherein the upper channel portions are spaced apart from each other.
However, Chen further discloses in Chen FIG. 23 and associated text each of the channel layers comprises: a lower channel portion in contact with the bit line (portions connecting semiconductor fins 123a/123b beneath source/drain regions 143a1/143b1 are in contact with source/drain regions 143a1 and 143b1 respectively (the source/drain regions correspond to channel contact regions of the bit line); please also refer to the following figure); and a plurality of upper channel portions on the lower channel portion (semiconductor fins 123a and 123b respectively), wherein the upper channel portions are spaced apart from each other (the portions of the semiconductor fins are spaced apart by gate structures 155a1 and 155b1 respectively).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the semiconductor structure of Kim, as previously modified by Chen, with the semiconductor fins and gate structures of Chen to provide a transistor structure where the plurality of upper fin structures are spaced apart by the gate structures to provide further control over both current and voltage bias of the semiconductor fins (Chen [0094]).
Regarding dependent claim 8, Kim, as modified by Chen, further discloses in Chen FIG. 20 and associated text a dielectric layer in contact with sidewalls of the upper channel portions and a top surface of the lower channel portion (gate dielectric layers 151a1 and 151b1 directly contact sidewalls of their respective upper and lower channel portions as depicted).
Regarding dependent claim 9, Kim, as modified by Chen, further discloses a third gate dielectric layer in contact with sidewalls of the upper channel portions and a top surface of the lower channel portion (gate dielectric layers 151a1 and 151b1 directly contact sidewalls of their respective upper and lower channel portions as depicted); and a third word line on the third gate dielectric layer (gate contact layers 153a1 and 153b1 would correspond to a third word line for their respective channel layers as combined).
Regarding independent claim 19, Kim discloses in Kim FIG. 88 and 95 and associated text a semiconductor device, comprising: a bit line (BL); a gate structure in contact with the bit line (please refer to the annotated figure illustrating the features which are interpreted as a gate structure, which is in (indirect) contact with bit line BL); channel layers that are spaced apart from each other with the gate structure between a first one of the channel layers and a second one of the channel layers (vertical channels VC are on either side of the gate structures); a landing pad electrically connected to at least one of the channel layers (bottom electrode contact 65); and a data storage pattern electrically connected to the landing pad (capacitor CA or other data storage elements disclosed in Kim [0110]), wherein the gate structure comprises: a first word line and a second word line (wordlines WL); a first gate dielectric layer in contact with a sidewall of the first word line (first and second gate insulators 32 and 42 are in contact with a sidewall of each wordline WL); a second gate dielectric layer in contact with a sidewall of the second word line (first and second gate insulators 32 and 42 are in contact with a sidewall of each wordline WL); and a gate capping layer in contact with the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer (interlayer dielectric layer 73 caps the gate structures and is in either direct or indirect contact with all aforementioned features).
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Kim does not explicitly disclose a support dielectric layer in contact with a top surface of the bit line, or the first and second word lines are spaced apart from each other in contact with a top surface of the support dielectric layer.
However, in the same field of endeavor, Chen discloses in Chen FIG. 20 and associated text a support dielectric layer in contact with a top surface of the bit line (bottom spacer layer 149 is a dielectric (Chen [0078]) in (indirect) contact with a top surface of source/drain structures 143 (corresponding to contact regions of a bit line)), and the first and second word lines are spaced apart from each other in contact with a top surface of the support dielectric layer (gate electrode layers 153a2 and 153b2 (corresponding to the first and second word lines claimed and their counterparts in Kim) are in (indirect) contact with a top surface of bottom spacer 149 and spaced apart as depicted)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim with the bottom spacer layer and corresponding structure of Chen to provide a transistor with gates isolated by the bottom spacer to cover and isolate underlying structures from the gate contacts.
Regarding dependent claim 20, Kim, as modified by Chen, further discloses in Kim FIG. 95 and associated text the landing pad is spaced apart from the first and second gate dielectric layers (bottom electrode contacts 65 are spaced apart from gate insulators 32/42).
Claims 6, 15, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, and further in view of Chen and Chuang.
Regarding dependent claim 6, Kim, as modified by Chen, further discloses in Kim FIG. 89 and associated text the semiconductor device of claim 1, further comprising a gate capping layer in contact with a top surface of the first gate dielectric layer, a top surface of the second gate dielectric layer (capping pattern 50 contacts top surfaces of the gate dielectric as depicted), a top surface of the first word line, a top surface of the second word line (interlayer dielectric layer 73 is in (indirect) contact with top surfaces of the wordlines WL). The combined reference does not explicitly disclose the gate capping layer is in contact with a top surface of a low-k material layer.
However, in the same field of endeavor, Chuang discloses in Chuang Fig. 1 and associated text a low-k material layer (dielectric material 102 is low-k (Chuang [0027])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the low-k material layer of Chuang with the semiconductor device of Kim, e.g. by replacing Kim’s FOX2 with the low-k material of Chuang’s 102, such that the gate capping layer is in contact with a top surface of a low-k material layer (73 is in contact with a top surface of FOX2, corresponding to the low-k material layer as combined) to reduce crosstalk and parasitic capacitance between wordlines (Chuang [0021], [0027]).
Regarding dependent claim 15, Kim, as modified by Chuang, discloses the semiconductor device of claim 10. The combined reference does not explicitly disclose each of the plurality of gate structures further comprises a support dielectric layer in contact with a top surface of the bit line, and wherein the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer are in contact with a top surface of the support dielectric layer.
However, in the same field of endeavor, Chen discloses in Chen FIG. 20 and associated text each of the plurality of gate structures further comprises a support dielectric layer in contact with a top surface of the bit line (bottom spacer layer 149 is a dielectric (Chen [0078]), which is in contact with bottom source/drain structures 143 (corresponding to contact regions of a bit line)), and wherein the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer are in contact with a top surface of the support dielectric layer (gate electrode layers 153a2/153b2 (corresponding to the first and second word lines claimed and their counterparts in Kim) and gate dielectric layers 151a2 and 151b2 (corresponding to the first and second gate dielectric layers claimed and their counterparts in Kim) are in contact with bottom spacer layer 149).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim, as modified by Chuang, with the bottom spacer layer and corresponding structure of Chen to provide a transistor with gates isolated by the bottom spacer to cover and isolate underlying structures from the gate contacts.
Regarding dependent claim 21, Kim, as modified by Chen, discloses the semiconductor device of claim 1. The combined reference does not explicitly disclose a width of a low-k material layer is wider than a width of the first word line.
However, in the same field of endeavor, Chuang discloses in Chuang Fig. 1 and associated text a width of a low-k material layer is wider than a width of the first word line (dielectric material 102 is low-k (Chuang [0027]) and clearly wider than metal line 108 corresponding to the first word line).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the low-k material layer of Chuang with the semiconductor device of Kim, as modified by Chen, e.g. by replacing Kim’s FOX2 with the low-k material of Chuang’s 102, such that a width of a low-k material layer is wider than a width of the first word line (Kim’s FOX2, corresponding to the low-k material layer as combined, is wider than Kim’s word lines WL) to reduce crosstalk and parasitic capacitance between word lines (Chuang [0021], [0027]).
Additionally, it would have been well-known to one of ordinary skill in the art before the effective filing date of the invention that the width of the dielectric material between word lines is inversely proportional to the parasitic capacitance between said lines and therefore would have recognized said width as a result effective variable. Therefore, it would have been further obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the low-k material layer of Kim, as modified by Chen and Chuang, to be wider than a width of the first word line. One would have chosen the width of the low-k dielectric layer according to a result effective variable to minimize parasitic capacitance between adjacent word lines. One would have been motivated to form the low-k dielectric layer to have a width wider than a width of the first word line to improve the efficiency of the device.
Regarding dependent claim 22, Kim, as modified by Chuang, discloses the semiconductor device of claim 10, wherein the low-k material fills in a space defined by the first word line, the second word line, the gate capping layer (FOX2, corresponding to the low-k material as combined, fills in the space defined by word lines WL and interlayer dielectric 73, corresponding to the gate capping layer). The combined reference does not explicitly disclose a support dielectric layer or that said support dielectric layer defines in part the aforementioned space filled by the low-k material.
However, in the same field of endeavor, Chen discloses in Chen FIG. 20 and associated text a support dielectric layer (bottom spacer layer 149 is a dielectric (Chen [0078])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim, as modified by Chuang, with the bottom spacer layer and corresponding structure of Chen positioned below and spanning between the word lines of Kim (as Chen’s 149 is positioned below and spanning between gate structures 155a and 155b) to provide a transistor with gates isolated by the bottom spacer to cover and isolate underlying structures from the gate contacts, which would act as a bound to the space which is filled by the low-k FOX2 of Kim, as modified by Chuang.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US-20190386135-A1, pertaining to a transistor with channel layers having separated upper channel regions; and
US-20210020762-A1, pertaining to a cylindrical transistor bisected into separate gate and channel regions by a trench.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu 8:30 AM - 6:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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