DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Claims 2-4, 12-14, 16, and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 February 2026.
Applicant has stated that claims 2-4, 12-14, 16, and 17 read on the elected species, however, the claimed features “a third gate dielectric layer” (specifically one which corresponds to GI3 as the claim limitations make clear, as opposed to the “third gate dielectric layer” of claim 9, corresponding to GI4) of claims 2-4 and 12-14 and “a cavity” of claims 16-17 are absent from the elected Species 5 as depicted in Fig. 26 and described in the election requirement.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 10 and 11 are rejected under 35 U.S.C. 102 (a)(1) and/or 102 (a)(2) as being anticipated by Kim et al. (US 20120299090 A1, hereinafter Kim).
Regarding independent claim 10, Kim discloses in Kim FIG. 88 and 95 and associated text a semiconductor device, comprising: a plurality of gate structures (please refer to the following figure); a channel layer between a first one of the plurality of gate structures and a second one of the plurality of gate structures (vertical channels VC); and a bit line in contact with the channel layer (BL), wherein each of the plurality of gate structures comprises: a first word line and a second word line that are spaced apart from each other (wordlines WL); a first gate dielectric layer on a first sidewall of the first word line (first and second gate insulators 32 and 42 are on a sidewall of each wordline WL); a second gate dielectric layer on a first sidewall of the second word line (first and second gate insulators 32 and 42 are on a sidewall of each wordline WL); and a gate capping layer in contact with a top surface of the first word line, a top surface of the second word line, a top surface of the first gate dielectric layer, and a top surface of the second gate dielectric layer (capping pattern 50 is in contact with all aforementioned features).
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Regarding dependent claim 11, Kim further discloses in Kim FIG. 95 and associated text the top surface of the first word line, the top surface of the second word line, the top surface of the first gate dielectric layer, and the top surface of the second gate dielectric layer are coplanar with each other (top surfaces of the aforementioned features are coplanar as depicted).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding dependent claim 18, Kim discloses the semiconductor device of claim 10, but does not explicitly disclose the top surface of the first word line, the top surface of the second word line, the top surface of the first gate dielectric layer, and the top surface of the second gate dielectric layer are at respective heights that are lower than a height of a top surface of the channel layer with respect to the bit line.
However, Kim discloses in Kim FIG. 3B and associated text a height of a top surface of the channel layer with respect to the bit line is higher than a bottom surface of part of the word lines (A bottom surface of the second impurity-implanted region 20 (corresponding to a top surface of the vertical chancel C/VC) may be higher than a bottom surface of the second sub-gate pattern SG2 (corresponding to a point somewhere between the top and bottom surfaces of the word lines), (Kim [0095])). Moreover, Kim recognizes the length of a channel (or height, in the case of vertical channels) as a result effective variable (a channel length may relatively increase to improve subthreshold characteristics and/or a threshold voltage distribution, (Kim [0101])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the vertical channels of Kim to be greater than the heights of the word lines and gate dielectric layers. One would have chosen the height of the channel according to a result effective variable to provide a transistor with threshold voltage or other characteristics suited to the application of the transistor. One would have been motivated to form the channel to have a height within the claimed range to improve threshold characteristics of the transistor.
Claims 1, 5-9, 15, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, and further in view of Chen et al. (US 20210408267 A1, hereinafter Chen).
Regarding independent claim 1, Kim discloses in Kim FIG. 88 and 95 and associated text a semiconductor device, comprising: a bit line (BL); a first word line and a second word line (wordlines WL; please refer to the following figure); a first gate dielectric layer on a first sidewall of the first word line (first and second gate insulators 32 and 42 are on a sidewalls of each wordline WL); a second gate dielectric layer on a first sidewall of the second word line (first and second gate insulators 32 and 42 are on a sidewalls of each wordline WL); and channel layers that are spaced apart from one another (vertical channels VC, spaced apart as depicted), wherein the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer are between a first one of the channel layers and a second one of the channel layers (each aforementioned feature is between vertical channels VC as depicted).
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Kim does not explicitly disclose a support dielectric layer on the bit line, the first word line and the second word line on the support dielectric layer, or the support dielectric layer is between the first and second channel layers.
However, in the same field of endeavor, Chen discloses in Chen FIG. 20 and associated text a support dielectric layer on the bit line (bottom spacer layer 149 is a dielectric (Chen [0078]) on source/drain structures 143 (corresponding to contact regions of a bit line)), the first word line and the second word line on the support dielectric layer (gate electrode layers 153a2 and 153b2 (corresponding to the first and second word lines claimed and their counterparts in Kim) are on bottom spacer 149), and the support dielectric layer is between the first and second channel layers (bottom spacer 149 is between semiconductor fins 123a and 123b (corresponding to the first and second channel layers claimed and their counterparts in Kim)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim with the bottom spacer layer and corresponding structure of Chen to provide a transistor with gates isolated by the bottom spacer to cover and isolate underlying structures from the gate contacts.
Regarding dependent claim 5, Kim, as modified by Chen, further discloses in Kim FIG. 89 and associated text a gate capping layer on the first word line and the second word line (capping pattern 50 is on the wordlines WL).
Regarding dependent claim 6, Kim, as modified by Chen, further discloses in Kim FIG. 89 and associated text the gate capping layer is in contact with a top surface of the first gate dielectric layer and a top surface of the second gate dielectric layer (capping pattern 50 contacts top surfaces of the gate dielectric as depicted).
Regarding dependent claim 7, Kim, as previously modified by Chen, discloses the semiconductor device of claim 1. However, as previously modified, the combination does not explicitly disclose each of the channel layers comprises: a lower channel portion in contact with the bit line; and a plurality of upper channel portions on the lower channel portion, wherein the upper channel portions are spaced apart from each other.
However, Chen further discloses in Chen FIG. 23 and associated text each of the channel layers comprises: a lower channel portion in contact with the bit line (portions connecting semiconductor fins 123a/123b beneath source/drain regions 143a1/143b1 are in contact with source/drain regions 143a1 and 143b1 respectively (the source/drain regions correspond to channel contact regions of the bit line); please also refer to the following figure); and a plurality of upper channel portions on the lower channel portion (semiconductor fins 123a and 123b respectively), wherein the upper channel portions are spaced apart from each other (the portions of the semiconductor fins are spaced apart by gate structures 155a1 and 155b1 respectively).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further combine the semiconductor structure of Kim, as previously modified by Chen, with the semiconductor fins and gate structures of Chen to provide a transistor structure where the plurality of upper fin structures are spaced apart by the gate structures to provide further control over both current and voltage bias of the semiconductor fins (Chen [0094]).
Regarding dependent claim 8, Kim, as modified by Chen, further discloses in Chen FIG. 20 and associated text a dielectric layer in contact with sidewalls of the upper channel portions and a top surface of the lower channel portion (gate dielectric layers 151a1 and 151b1 directly contact sidewalls of their respective upper and lower channel portions as depicted).
Regarding dependent claim 9, Kim, as modified by Chen, further discloses a third gate dielectric layer in contact with sidewalls of the upper channel portions and a top surface of the lower channel portion (gate dielectric layers 151a1 and 151b1 directly contact sidewalls of their respective upper and lower channel portions as depicted); and a third word line on the third gate dielectric layer (gate contact layers 153a1 and 153b1 would correspond to a third word line for their respective channel layers as combined).
Regarding dependent claim 15, Kim discloses the semiconductor device of claim 10. Kim does not explicitly disclose each of the plurality of gate structures further comprises a support dielectric layer in contact with a top surface of the bit line, and wherein the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer are in contact with a top surface of the support dielectric layer.
However, in the same field of endeavor, Chen discloses in Chen FIG. 20 and associated text each of the plurality of gate structures further comprises a support dielectric layer in contact with a top surface of the bit line (bottom spacer layer 149 is a dielectric (Chen [0078]), which is in contact with bottom source/drain structures 143 (corresponding to contact regions of a bit line)), and wherein the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer are in contact with a top surface of the support dielectric layer (gate electrode layers 153a2/153b2 (corresponding to the first and second word lines claimed and their counterparts in Kim) and gate dielectric layers 151a2 and 151b2 (corresponding to the first and second gate dielectric layers claimed and their counterparts in Kim) are in contact with bottom spacer layer 149).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim with the bottom spacer layer and corresponding structure of Chen to provide a transistor with gates isolated by the bottom spacer to cover and isolate underlying structures from the gate contacts.
Regarding independent claim 19, Kim discloses in Kim FIG. 88 and 95 and associated text a semiconductor device, comprising: a bit line (BL); a gate structure on the bit line (please refer to the following figure); channel layers that are spaced apart from each other with the gate structure between a first one of the channel layers and a second one of the channel layers (vertical channels VC are on either side of the gate structures); a landing pad electrically connected to at least one of the channel layers (bottom electrode contact 65); and a data storage pattern electrically connected to the landing pad (capacitor CA or other data storage elements disclosed in Kim [0110]), wherein the gate structure comprises: a first word line and a second word line (wordlines WL); a first gate dielectric layer on a sidewall of the first word line (first and second gate insulators 32 and 42 are on a sidewall of each wordline WL); a second gate dielectric layer on a sidewall of the second word line (first and second gate insulators 32 and 42 are on a sidewall of each wordline WL); and a gate capping layer in contact with the first word line, the second word line, the first gate dielectric layer, and the second gate dielectric layer (interlayer dielectric layer 73 caps the gate structures and is in either direct or indirect contact with all aforementioned features).
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Kim does not explicitly disclose a support dielectric layer on the bit line, or the first and second word lines are spaced apart from each other on the support dielectric layer.
However, in the same field of endeavor, Chen discloses in Chen FIG. 20 and associated text a support dielectric layer on the bit line (bottom spacer layer 149 is a dielectric (Chen [0078]) on source/drain structures 143 (corresponding to contact regions of a bit line)), and the first and second word lines are spaced apart from each other on the support dielectric layer (gate electrode layers 153a2 and 153b2 (corresponding to the first and second word lines claimed and their counterparts in Kim) are on bottom spacer 149 and spaced apart as depicted)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim with the bottom spacer layer and corresponding structure of Chen to provide a transistor with gates isolated by the bottom spacer to cover and isolate underlying structures from the gate contacts.
Regarding dependent claim 20, Kim, as modified by Chen, further discloses in Kim FIG. 95 and associated text the landing pad is spaced apart from the first and second gate dielectric layers (bottom electrode contacts 65 are spaced apart from gate insulators 32/42).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US-20190386135-A1, pertaining to a transistor with channel layers having separated upper channel regions; and
US-20210020762-A1, pertaining to a cylindrical transistor bisected into separate gate and channel regions by a trench.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu 8:30 AM - 6:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897