DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term "substantially" in claims 3 and 17, is a relative term which renders the claim indefinite. The term “substantially" was found indefinite where was close prior art and there was nothing in the specification, prosecution history, or the prior art to provide any indication as to what range of specific activity is covered by the term “substantially.”
For purpose of compact prosecution, term “substantially uniform” will be treated as if it were “not necessarily uniform.”
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 recites the limitation of "the carrier concentration decreases both upward and downward in a depth direction of the semiconductor device, from a peak concentration thereof at a peak position to a pre-determined concentration at a first depth position and a second depth position respectively above and below the peak position, a first width being a distance in the depth direction between the first depth position and the peak position, a second width being a distance in the depth direction between the peak position and the second depth position, the first width being larger than the second width" in lines 16-22. The meaning of the claim term is indefinite because the claim term is not used or defined in the specification.
Claim 6 recites the limitation “pre-determined concentration is a half of the peak concentration” in lines 2-3. The meaning of the claim term is indefinite because the claim term is not used or defined in the specification.
Claim 7 recites the limitation “pre-determined concentration is 1/e times the peak concentration” in lines 2-3. The meaning of the claim term is indefinite because the claim term is not used or defined in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
Claim(s) 1-23 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Nemoto et al. ( WO 2011/052787 A1, hereinafter refer to Nemoto).
U.S. 2012/0267681 A1 (hereinafter refer to Nemoto) is relied upon solely for the English language translation of WO 2011/052787 A1.
Regarding Claim 1: Nemoto discloses a semiconductor device (see Nemoto, Figs.13 as shown below and ¶ [0001]) comprising:
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a semiconductor substrate having a first main surface and a second main surface, the semiconductor substrate having an n-type drift layer (21) provided therein (see Nemoto, Figs.13 as shown above);
a p-type layer (22) provided between the first main surface of the semiconductor substrate and the drift layer (21) (see Nemoto, Figs.13 as shown above); and
an n-type high-concentration layer (26) provided between the second main surface of the semiconductor substrate and the drift layer (21), the n-type high-concentration layer (26) including a plurality of buffer layers (see Nemoto, Figs.13 as shown above),
wherein a carrier concentration of the semiconductor device is higher in the n-type high- concentration layer (26) than in the semiconductor substrate (see Nemoto, Figs.13 as shown above), and
in one of the plurality of buffer layers (26), the carrier concentration decreases both upward and downward in a depth direction of the semiconductor device, from a peak concentration thereof at a peak position (peak position at a distance of 110µm from the first main surface) to a pre-determined concentration at a first depth position (the first depth position is a position up to a peak position of 110µm from the first main surface) and a second depth position (the second depth position is a position up to a distance of 3µm from the peak position of 110µm) respectively above and below the peak position, a first width being a distance in the depth direction between the first depth position and the peak position, a second width being a distance in the depth direction between the peak position and the second depth position, the first width being larger than the second width (see Nemoto, Figs.13 as shown above).
Regarding Claim 2: Nemoto discloses a semiconductor device as set forth in claim 1 as above. Nemoto further teaches wherein the n- type high-concentration layer (26) includes hydrogen as a donor (see Nemoto, Figs.13 as shown above and ¶ [0004]).
Regarding Claim 3: Nemoto discloses a semiconductor device as set forth in claim 2 as above. Nemoto further teaches wherein the carrier concentration is substantially uniform in the drift layer (21) (see Nemoto, Figs.13 as shown above).
Regarding Claim 4: Nemoto discloses a semiconductor device as set forth in claim 2 as above. Nemoto further teaches wherein the carrier concentration has a peak concentration in each of the plurality of buffer layers (26), and decrease from each peak concentration asymmetrically upward and downward in the depth direction (see Nemoto, Figs.13 as shown above).
Regarding Claim 5: Nemoto discloses a semiconductor device as set forth in claim 2 as above. Nemoto further teaches wherein the carrier concentration in the n-type high-concentration layer is higher than 1x1014/cm3 (see Nemoto, Figs.13 as shown above).
Regarding Claim 6: Nemoto discloses a semiconductor device as set forth in claim 2 as above. Nemoto further teaches wherein the pre-determined concentration is a half of the peak concentration (see Nemoto, Figs.13 as shown above).
Regarding Claim 7: Nemoto discloses a semiconductor device as set forth in claim 2 as above. Nemoto further teaches wherein the pre-determined concentration is 1/e times the peak concentration (see Nemoto, Figs.13 as shown above).
Regarding Claim 8: Nemoto discloses a semiconductor device as set forth in claim 2 as above. Nemoto further teaches wherein the plurality of buffer layers (26) include, in the depth direction from the first main surface to the second main surface of the semiconductor substrate (see Nemoto, Figs.13 as shown above),
a deepest buffer layer (26), at least one intermediate buffer layer (26), and a shallowest buffer layer (26) (see Nemoto, Figs.13 as shown above).
Regarding Claim 9: Nemoto discloses a semiconductor device as set forth in claim 8 as above. Nemoto further teaches wherein the carrier concentration has a peak concentration in each of the plurality of buffer layers (26); and
in the semiconductor device:
Y=WO-(Z+xj); and
Z=αWO,
wherein α is equal to or greater than 0.4 and equal to or less than 0.8,
WO is a distance between the first main surface and the second main surface of the semiconductor substrate in the depth direction,
xi is a thickness of the p-type layer (22) in the depth direction,
Z is a distance in the depth direction from an interface between the p-type layer (22) and the drift layer (21) to the deepest buffer layer (26), and
Y is a distance in the depth direction from the second main surface of the semiconductor substrate to the peak position of the shallowest buffer layer (26) (see Nemoto, Figs.13 as shown above).
Note: the discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.
Regarding Claim 10: Nemoto discloses a semiconductor device as set forth in claim 8 as above. Nemoto further teaches wherein the semiconductor device is a diode (see Nemoto, Figs.13 as shown above), and
the semiconductor device further includes an n-type cathode layer (23) between the second main surface of the semiconductor substrate and the shallowest buffer layer (26) (see Nemoto, Figs.13 as shown above).
Regarding Claim 11: Nemoto discloses a semiconductor device as set forth in claim 8 as above. Nemoto further teaches wherein the semiconductor device is an Insulated Gate Bipolar Transistor (see Nemoto, Figs.13 as shown above), and
the semiconductor device further includes a p-type collector layer (28) between the second main surface of the semiconductor substrate and the shallowest buffer layer (26) (see Nemoto, Figs.13 as shown above).
Regarding Claim 12: Nemoto discloses a semiconductor device as set forth in claim 1 as above. Nemoto further teaches wherein the carrier concentration is the same in the drift layer (21) and in the semiconductor substrate (see Nemoto, Figs.13 as shown above).
Regarding Claim 13: Nemoto discloses a semiconductor device as set forth in claim 12 as above. Nemoto further teaches wherein the drift layer (21) is in direct contact with the p-type layer (22) and the n-type high-concentration layer (26) (see Nemoto, Figs.13 as shown above).
Regarding Claim 14: Nemoto discloses a semiconductor device as set forth in claim 1 as above. Nemoto further teaches wherein a distribution of the carrier concentration, of the semiconductor device has a plurality of inflection points between the plurality of buffer layers (26), the plurality of inflection points corresponding to a plurality of carrier concentrations that become lower in the depth direction from the second main surface toward the first main surface of the semiconductor substrate (see Nemoto, Figs.13 as shown above).
Regarding Claim 15: Nemoto discloses a semiconductor device as set forth in claim 6 as above. Nemoto further teaches wherein the n- type high-concentration layer further includes a carrier storage regions between adjacent two of the plurality of buffer layers (26) (see Nemoto, Figs.13 as shown above).
Regarding Claim 16: Nemoto discloses a semiconductor device as set forth in claim 15 as above. Nemoto further teaches wherein a width of the carrier storage region is longer than a half width of each of the buffer layers (26) (see Nemoto, Figs.13 as shown above).
Regarding Claim 17: Nemoto discloses a semiconductor device as set forth in claim 15 as above. Nemoto further teaches wherein the carrier concentration is substantially uniform in the carrier storage region (see Nemoto, Figs.13 as shown above).
Regarding Claim 18: Nemoto discloses a semiconductor device as set forth in claim 1 as above. Nemoto further teaches wherein an active region and a junction termination structure surrounding the active region (see Nemoto, Figs.13 as shown above),
wherein the n-type high-concentration layer is provided from the active region to the junction termination structure in a lateral direction (see Nemoto, Figs.13 as shown above).
Note: patentability of a product does not depend on its method of production.
Regarding Claim 19: Nemoto discloses a semiconductor device as set forth in claim 18 as above. Nemoto further teaches wherein the junction termination structure includes a ring-shaped p-type layer (22) provided in the semiconductor substrate at the first main surface thereof (see Nemoto, Figs.13 as shown above).
Note: the configuration of the claimed p-type layer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed p-type layer was significant.
Regarding Claim 20: Nemoto discloses a semiconductor device as set forth in claim 19 as above. Nemoto further teaches wherein the junction termination structure further includes an electrode (24) connected to the ring-shaped p-type layer (22) (see Nemoto, Figs.13 as shown above).
Regarding Claim 21: Nemoto discloses a semiconductor device as set forth in claim 8 as above. Nemoto further teaches wherein said one buffer layer (26) is the deepest buffer layer (see Nemoto, Figs.13 as shown above).
Regarding Claim 22: Nemoto discloses a semiconductor device as set forth in claim 1 as above. Nemoto further teaches wherein the semiconductor device is a diode (see Nemoto, Figs.13 as shown above).
Regarding Claim 23: Nemoto discloses a semiconductor device as set forth in claim 1 as above. Nemoto further teaches wherein the semiconductor device is an Insulated Gate Bipolar Transistor (see Nemoto, Figs.13 as shown above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812